1 /*- 2 * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol 3 * controller RISC processor CL-CD2400/2401. 4 * 5 * Copyright (C) 1994-2000 Cronyx Engineering. 6 * Author: Serge Vakulenko, <vak@cronyx.ru> 7 * 8 * This software is distributed with NO WARRANTIES, not even the implied 9 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 10 * 11 * Authors grant any other persons or organisations permission to use 12 * or modify this software as long as this message is kept with the software, 13 * all derivative works or modified versions. 14 * 15 * Cronyx Id: cxreg.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $ 16 * $FreeBSD$ 17 */ 18 #define REVCL_MIN 7 /* CD2400 min. revision number G */ 19 #define REVCL_MAX 13 /* CD2400 max. revision number M */ 20 #define REVCL31_MIN 0x33 /* CD2431 min. revision number C */ 21 #define REVCL31_MAX 0x34 /* CD2431 max. revision number D */ 22 23 #define BRD_INTR_LEVEL 0x5a /* interrupt level (arbitrary PILR value) */ 24 25 #define CS0(p) ((p) | 0x8000) /* chip select 0 */ 26 #define CS1(p) ((p) | 0xc000) /* chip select 1 */ 27 #define CS1A(p) ((p) | 0x8010) /* chip select 1 for agp-compatible models */ 28 #define BSR(p) (p) /* board status register, read only */ 29 #define BCR0(p) (p) /* board command register 0, write only */ 30 #define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */ 31 32 /* 33 * For Sigma-800 only. 34 */ 35 #define BDET(p) ((p) | 0x2000) /* board detection register, read only */ 36 #define BCR2(p) ((p) | 0x4000) /* board command register 2, write only */ 37 38 /* 39 * Chip register address, B is chip base port, R is chip register number. 40 */ 41 #define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf))) 42 43 /* 44 * Interrupt acknowledge register, P is board port, L is interrupt level, 45 * as prodrammed in PILR. 46 */ 47 #define IACK(p,l) (R(p,l) | 0x4000) 48 49 /* 50 * Global registers. 51 */ 52 #define GFRCR(b) R(b,0x82) /* global firmware revision code register */ 53 #define CAR(b) R(b,0xec) /* channel access register */ 54 55 /* 56 * Option registers. 57 */ 58 #define CMR(b) R(b,0x18) /* channel mode register */ 59 #define COR1(b) R(b,0x13) /* channel option register 1 */ 60 #define COR2(b) R(b,0x14) /* channel option register 2 */ 61 #define COR3(b) R(b,0x15) /* channel option register 3 */ 62 #define COR4(b) R(b,0x16) /* channel option register 4 */ 63 #define COR5(b) R(b,0x17) /* channel option register 5 */ 64 #define COR6(b) R(b,0x1b) /* channel option register 6 */ 65 #define COR7(b) R(b,0x04) /* channel option register 7 */ 66 #define SCHR1(b) R(b,0x1c) /* special character register 1 */ 67 #define SCHR2(b) R(b,0x1d) /* special character register 2 */ 68 #define SCHR3(b) R(b,0x1e) /* special character register 3 */ 69 #define SCHR4(b) R(b,0x1f) /* special character register 4 */ 70 #define SCRL(b) R(b,0x20) /* special character range low */ 71 #define SCRH(b) R(b,0x21) /* special character range high */ 72 #define LNXT(b) R(b,0x2d) /* LNext character */ 73 #define RFAR1(b) R(b,0x1c) /* receive frame address register 1 */ 74 #define RFAR2(b) R(b,0x1d) /* receive frame address register 2 */ 75 #define RFAR3(b) R(b,0x1e) /* receive frame address register 3 */ 76 #define RFAR4(b) R(b,0x1f) /* receive frame address register 4 */ 77 #define CPSR(b) R(b,0xd4) /* CRC polynomial select register */ 78 79 /* 80 * Bit rate and clock option registers. 81 */ 82 #define RBPR(b) R(b,0xc9) /* receive baud rate period register */ 83 #define RCOR(b) R(b,0xca) /* receive clock option register */ 84 #define TBPR(b) R(b,0xc1) /* transmit baud rate period register */ 85 #define TCOR(b) R(b,0xc2) /* receive clock option register */ 86 87 /* 88 * Channel command and status registers. 89 */ 90 #define CCR(b) R(b,0x10) /* channel command register */ 91 #define STCR(b) R(b,0x11) /* special transmit command register */ 92 #define CSR(b) R(b,0x19) /* channel status register */ 93 #define MSVR(b) R(b,0xdc) /* modem signal value register */ 94 #define MSVR_RTS(b) R(b,0xdc) /* modem RTS setup register */ 95 #define MSVR_DTR(b) R(b,0xdd) /* modem DTR setup register */ 96 97 /* 98 * Interrupt registers. 99 */ 100 #define LIVR(b) R(b,0x0a) /* local interrupt vector register */ 101 #define IER(b) R(b,0x12) /* interrupt enable register */ 102 #define LICR(b) R(b,0x25) /* local interrupting channel register */ 103 #define STK(b) R(b,0xe0) /* stack register */ 104 105 /* 106 * Receive interrupt registers. 107 */ 108 #define RPILR(b) R(b,0xe3) /* receive priority interrupt level register */ 109 #define RIR(b) R(b,0xef) /* receive interrupt register */ 110 #define RISR(b) R(b,0x8a) /* receive interrupt status register */ 111 #define RISRL(b) R(b,0x8a) /* receive interrupt status register low */ 112 #define RISRH(b) R(b,0x8b) /* receive interrupt status register high */ 113 #define RFOC(b) R(b,0x33) /* receive FIFO output count */ 114 #define RDR(b) R(b,0xf8) /* receive data register */ 115 #define REOIR(b) R(b,0x87) /* receive end of interrupt register */ 116 117 /* 118 * Transmit interrupt registers. 119 */ 120 #define TPILR(b) R(b,0xe2) /* transmit priority interrupt level reg */ 121 #define TIR(b) R(b,0xee) /* transmit interrupt register */ 122 #define TISR(b) R(b,0x89) /* transmit interrupt status register */ 123 #define TFTC(b) R(b,0x83) /* transmit FIFO transfer count */ 124 #define TDR(b) R(b,0xf8) /* transmit data register */ 125 #define TEOIR(b) R(b,0x86) /* transmit end of interrupt register */ 126 127 /* 128 * Modem interrupt registers. 129 */ 130 #define MPILR(b) R(b,0xe1) /* modem priority interrupt level register */ 131 #define MIR(b) R(b,0xed) /* modem interrupt register */ 132 #define MISR(b) R(b,0x88) /* modem/timer interrupt status register */ 133 #define MEOIR(b) R(b,0x85) /* modem end of interrupt register */ 134 135 /* 136 * DMA registers. 137 */ 138 #define DMR(b) R(b,0xf4) /* DMA mode register */ 139 #define BERCNT(b) R(b,0x8d) /* bus error retry count */ 140 #define DMABSTS(b) R(b,0x1a) /* DMA buffer status */ 141 142 /* 143 * DMA receive registers. 144 */ 145 #define ARBADRL(b) R(b,0x40) /* A receive buffer address lower */ 146 #define ARBADRU(b) R(b,0x42) /* A receive buffer address upper */ 147 #define BRBADRL(b) R(b,0x44) /* B receive buffer address lower */ 148 #define BRBADRU(b) R(b,0x46) /* B receive buffer address upper */ 149 #define ARBCNT(b) R(b,0x48) /* A receive buffer byte count */ 150 #define BRBCNT(b) R(b,0x4a) /* B receive buffer byte count */ 151 #define ARBSTS(b) R(b,0x4c) /* A receive buffer status */ 152 #define BRBSTS(b) R(b,0x4d) /* B receive buffer status */ 153 #define RCBADRL(b) R(b,0x3c) /* receive current buffer address lower */ 154 #define RCBADRU(b) R(b,0x3e) /* receive current buffer address upper */ 155 156 /* 157 * DMA transmit registers. 158 */ 159 #define ATBADRL(b) R(b,0x50) /* A transmit buffer address lower */ 160 #define ATBADRU(b) R(b,0x52) /* A transmit buffer address upper */ 161 #define BTBADRL(b) R(b,0x54) /* B transmit buffer address lower */ 162 #define BTBADRU(b) R(b,0x56) /* B transmit buffer address upper */ 163 #define ATBCNT(b) R(b,0x58) /* A transmit buffer byte count */ 164 #define BTBCNT(b) R(b,0x5a) /* B transmit buffer byte count */ 165 #define ATBSTS(b) R(b,0x5c) /* A transmit buffer status */ 166 #define BTBSTS(b) R(b,0x5d) /* B transmit buffer status */ 167 #define TCBADRL(b) R(b,0x38) /* transmit current buffer address lower */ 168 #define TCBADRU(b) R(b,0x3a) /* transmit current buffer address upper */ 169 170 /* 171 * Timer registers. 172 */ 173 #define TPR(b) R(b,0xd8) /* timer period register */ 174 #define RTPR(b) R(b,0x26) /* receive timeout period register */ 175 #define RTPRL(b) R(b,0x26) /* receive timeout period register low */ 176 #define RTPTH(b) R(b,0x27) /* receive timeout period register high */ 177 #define GT1(b) R(b,0x28) /* general timer 1 */ 178 #define GT1L(b) R(b,0x28) /* general timer 1 low */ 179 #define GT1H(b) R(b,0x29) /* general timer 1 high */ 180 #define GT2(b) R(b,0x2a) /* general timer 2 */ 181 #define TTR(b) R(b,0x2a) /* transmit timer register */ 182 183 /* 184 * Board status register bits, for all models. 185 */ 186 #define BSR_NOINTR 0x01 /* no interrupt pending flag */ 187 #define BSR_NOCHAIN 0x80 /* no daisy chained board, all but Sigma-22 */ 188 189 /* 190 * For old Sigmas only. 191 */ 192 #define BSR_VAR_MASK 0x66 /* adapter variant mask */ 193 #define BSR_OSC_MASK 0x18 /* oscillator frequency mask */ 194 #define BSR_OSC_20 0x18 /* 20 MHz */ 195 #define BSR_OSC_18432 0x10 /* 18.432 MHz */ 196 197 #define BSR_NODSR(n) (0x100 << (n)) /* DSR from channels 0-3, inverted */ 198 #define BSR_NOCD(n) (0x1000 << (n)) /* CD from channels 0-3, inverted */ 199 200 /* 201 * Board status register bits for Sigma-2x. 202 */ 203 #define BSR2X_OSC_33 0x08 /* oscillator 33/20 MHz bit */ 204 #define BSR2X_VAR_MASK 0x30 /* Sigma-2x variant mask */ 205 206 /* 207 * Board status register bits for Sigma-800. 208 */ 209 #define BSR800_NU0 0x02 /* no channels 0-3 installed */ 210 #define BSR800_NU1 0x04 /* no channels 4-7 installed */ 211 #define BSR800_LERR 0x08 /* firmware load error */ 212 #define BSR800_MIRQ 0x10 /* modem IRQ active */ 213 #define BSR800_TIRQ 0x20 /* transmit IRQ active */ 214 #define BSR800_RIRQ 0x40 /* receive IRQ active */ 215 216 #define BDET_IB 0x08 /* identification bit */ 217 #define BDET_IB_NEG 0x80 /* negated identification bit */ 218 219 /* 220 * Sigma-800 control register 2 bits. 221 */ 222 #define BCR2_BUS0 0x01 /* bus timing control */ 223 #define BCR2_BUS1 0x02 /* bus timing control */ 224 #define BCR2_TMS 0x08 /* firmware download signal */ 225 #define BCR2_TDI 0x80 /* firmware download signal */ 226 227 /* 228 * Board revision mask. 229 */ 230 #define BSR_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN) 231 #define BSR2X_REV_MASK (BSR_OSC_MASK|BSR_VAR_MASK) 232 233 /* 234 * Sigma-2x variants. 235 */ 236 #define CRONYX_22 0x20 237 #define CRONYX_24 0x00 238 239 /* 240 * Sigma-XXX variants. 241 */ 242 #define CRONYX_100 0x64 243 #define CRONYX_400 0x62 244 #define CRONYX_500 0x60 245 #define CRONYX_410 0x24 246 #define CRONYX_810 0x20 247 #define CRONYX_410s 0x04 248 #define CRONYX_810s 0x00 249 #define CRONYX_440 0x44 250 #define CRONYX_840 0x40 251 #define CRONYX_401 0x26 252 #define CRONYX_801 0x22 253 #define CRONYX_401s 0x06 254 #define CRONYX_801s 0x02 255 #define CRONYX_404 0x46 256 #define CRONYX_703 0x42 257 258 /* 259 * Board control register 0 bits. 260 */ 261 #define BCR0_IRQ_DIS 0x00 /* no interrupt generated */ 262 #define BCR0_IRQ_3 0x01 /* select IRQ number 3 */ 263 #define BCR0_IRQ_5 0x02 /* select IRQ number 5 */ 264 #define BCR0_IRQ_7 0x03 /* select IRQ number 7 */ 265 #define BCR0_IRQ_10 0x04 /* select IRQ number 10 */ 266 #define BCR0_IRQ_11 0x05 /* select IRQ number 11 */ 267 #define BCR0_IRQ_12 0x06 /* select IRQ number 12 */ 268 #define BCR0_IRQ_15 0x07 /* select IRQ number 15 */ 269 #define BCR0_IRQ_MASK 0x07 /* irq select mask */ 270 271 #define BCR0_DMA_DIS 0x00 /* no interrupt generated */ 272 #define BCR0_DMA_5 0x10 /* select DMA channel 5 */ 273 #define BCR0_DMA_6 0x20 /* select DMA channel 6 */ 274 #define BCR0_DMA_7 0x30 /* select DMA channel 7 */ 275 #define BCR0_DMA_MASK 0x30 /* drq select mask */ 276 277 /* For old Sigmas only. */ 278 #define BCR0_NORESET 0x08 /* CD2400 reset flag (inverted) */ 279 280 #define BCR0_UM_ASYNC 0x00 /* channel 0 mode - async */ 281 #define BCR0_UM_SYNC 0x80 /* channel 0 mode - sync */ 282 #define BCR0_UI_RS232 0x00 /* channel 0 interface - RS-232 */ 283 #define BCR0_UI_RS449 0x40 /* channel 0 interface - RS-449/V.35 */ 284 #define BCR0_UMASK 0xc0 /* channel 0 interface mask */ 285 286 /* For Sigma-22 only. */ 287 #define BCR02X_FAST 0x40 /* fast bus timing */ 288 #define BCR02X_LED 0x80 /* LED control */ 289 290 /* For Sigma-800 only. */ 291 #define BCR0800_TCK 0x80 /* firmware download signal */ 292 293 /* 294 * Board control register 1 bits. 295 */ 296 /* For old Sigmas only. */ 297 #define BCR1_DTR(n) (0x100 << (n)) /* DTR for channels 0-3 sync */ 298 299 /* For Sigma-800 only. */ 300 #define BCR1800_DTR(n) (1 << ((n) & 7)) /* DTR for channels 0-7 sync */ 301 302 /* 303 * Channel commands (CCR). 304 */ 305 #define CCR_CLRCH 0x40 /* clear channel */ 306 #define CCR_INITCH 0x20 /* initialize channel */ 307 #define CCR_RSTALL 0x10 /* reset all channels */ 308 #define CCR_ENTX 0x08 /* enable transmitter */ 309 #define CCR_DISTX 0x04 /* disable transmitter */ 310 #define CCR_ENRX 0x02 /* enable receiver */ 311 #define CCR_DISRX 0x01 /* disable receiver */ 312 #define CCR_CLRT1 0xc0 /* clear timer 1 */ 313 #define CCR_CLRT2 0xa0 /* clear timer 2 */ 314 #define CCR_CLRRCV 0x90 /* clear receiver */ 315 #define CCR_CLRTX 0x88 /* clear transmitter */ 316 317 /* 318 * Interrupt enable register (IER) bits. 319 */ 320 #define IER_MDM 0x80 /* modem status changed */ 321 #define IER_RET 0x20 /* receive exception timeout */ 322 #define IER_RXD 0x08 /* data received */ 323 #define IER_TIMER 0x04 /* timer expired */ 324 #define IER_TXMPTY 0x02 /* transmitter empty */ 325 #define IER_TXD 0x01 /* data transmitted */ 326 327 /* 328 * Modem signal values register bits (MSVR). 329 */ 330 #define MSV_DSR 0x80 /* state of Data Set Ready input */ 331 #define MSV_CD 0x40 /* state of Carrier Detect input */ 332 #define MSV_CTS 0x20 /* state of Clear to Send input */ 333 #define MSV_TXCOUT 0x10 /* TXCout/DTR pin output flag */ 334 #define MSV_PORTID 0x04 /* device is CL-CD2401 (not 2400) */ 335 #define MSV_DTR 0x02 /* state of Data Terminal Ready output */ 336 #define MSV_RTS 0x01 /* state of Request to Send output */ 337 #define MSV_BITS "\20\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr" 338 339 /* 340 * DMA buffer status register bits (DMABSTS). 341 */ 342 #define DMABSTS_TDALIGN 0x80 /* internal data alignment in transmit FIFO */ 343 #define DMABSTS_RSTAPD 0x40 /* reset append mode */ 344 #define DMABSTS_CRTTBUF 0x20 /* internal current transmit buffer in use */ 345 #define DMABSTS_APPEND 0x10 /* append buffer is in use */ 346 #define DMABSTS_NTBUF 0x08 /* next transmit buffer is B (not A) */ 347 #define DMABSTS_TBUSY 0x04 /* current transmit buffer is in use */ 348 #define DMABSTS_NRBUF 0x02 /* next receive buffer is B (not A) */ 349 #define DMABSTS_RBUSY 0x01 /* current receive buffer is in use */ 350 351 /* 352 * Buffer status register bits ([AB][RT]BSTS). 353 */ 354 #define BSTS_BUSERR 0x80 /* bus error */ 355 #define BSTS_EOFR 0x40 /* end of frame */ 356 #define BSTS_EOBUF 0x20 /* end of buffer */ 357 #define BSTS_APPEND 0x08 /* append mode */ 358 #define BSTS_INTR 0x02 /* interrupt required */ 359 #define BSTS_OWN24 0x01 /* buffer is (free to be) used by CD2400 */ 360 #define BSTS_BITS "\20\1own24\2intr\4append\6eobuf\7eofr\10buserr" 361 362 /* 363 * Receive interrupt status register (RISR) bits. 364 */ 365 #define RIS_OVERRUN 0x0008 /* overrun error */ 366 #define RIS_BB 0x0800 /* buffer B status (not A) */ 367 #define RIS_EOBUF 0x2000 /* end of buffer reached */ 368 #define RIS_EOFR 0x4000 /* frame reception complete */ 369 #define RIS_BUSERR 0x8000 /* bus error */ 370 371 #define RISH_CLRDCT 0x0001 /* X.21 clear detect */ 372 #define RISH_RESIND 0x0004 /* residual indication */ 373 #define RISH_CRCERR 0x0010 /* CRC error */ 374 #define RISH_RXABORT 0x0020 /* abort sequence received */ 375 #define RISH_EOFR 0x0040 /* complete frame received */ 376 #define RISH_BITS "\20\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr" 377 378 #define RISA_BREAK 0x0001 /* break signal detected */ 379 #define RISA_FRERR 0x0002 /* frame error (bad stop bits) */ 380 #define RISA_PARERR 0x0004 /* parity error */ 381 #define RISA_SCMASK 0x0070 /* special character detect mask */ 382 #define RISA_SCHR1 0x0010 /* special character 1 detected */ 383 #define RISA_SCHR2 0x0020 /* special character 2 detected */ 384 #define RISA_SCHR3 0x0030 /* special character 3 detected */ 385 #define RISA_SCHR4 0x0040 /* special character 4 detected */ 386 #define RISA_SCRANGE 0x0070 /* special character in range detected */ 387 #define RISA_TIMEOUT 0x0080 /* receive timeout, no data */ 388 #define RISA_BITS "\20\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr" 389 390 #define RISB_CRCERR 0x0010 /* CRC error */ 391 #define RISB_RXABORT 0x0020 /* abort sequence received */ 392 #define RISB_EOFR 0x0040 /* complete frame received */ 393 394 #define RISX_LEADCHG 0x0001 /* CTS lead change */ 395 #define RISX_PARERR 0x0004 /* parity error */ 396 #define RISX_SCMASK 0x0070 /* special character detect mask */ 397 #define RISX_SCHR1 0x0010 /* special character 1 detected */ 398 #define RISX_SCHR2 0x0020 /* special character 2 detected */ 399 #define RISX_SCHR3 0x0030 /* special character 3 detected */ 400 #define RISX_ALLZERO 0x0040 /* all 0 condition detected */ 401 #define RISX_ALLONE 0x0050 /* all 1 condition detected */ 402 #define RISX_ALTOZ 0x0060 /* alternating 1 0 condition detected */ 403 #define RISX_SYN 0x0070 /* SYN detected */ 404 #define RISX_LEAD 0x0080 /* leading value */ 405 406 /* 407 * Channel mode register (CMR) bits. 408 */ 409 #define CMR_RXDMA 0x80 /* DMA receive transfer mode */ 410 #define CMR_TXDMA 0x40 /* DMA transmit transfer mode */ 411 #define CMR_HDLC 0x00 /* HDLC protocol mode */ 412 #define CMR_BISYNC 0x01 /* BISYNC protocol mode */ 413 #define CMR_ASYNC 0x02 /* ASYNC protocol mode */ 414 #define CMR_X21 0x03 /* X.21 protocol mode */ 415 416 /* 417 * Modem interrupt status register (MISR) bits. 418 */ 419 #define MIS_CDSR 0x80 /* DSR changed */ 420 #define MIS_CCD 0x40 /* CD changed */ 421 #define MIS_CCTS 0x20 /* CTS changed */ 422 #define MIS_CGT2 0x02 /* GT2 timer expired */ 423 #define MIS_CGT1 0x01 /* GT1 timer expired */ 424 #define MIS_BITS "\20\1gt1\2gt2\6ccts\7ccd\10cdsr" 425 426 /* 427 * Transmit interrupt status register (TISR) bits. 428 */ 429 #define TIS_BUSERR 0x80 /* Bus error */ 430 #define TIS_EOFR 0x40 /* End of frame */ 431 #define TIS_EOBUF 0x20 /* end of transmit buffer reached */ 432 #define TIS_UNDERRUN 0x10 /* transmit underrun */ 433 #define TIS_BB 0x08 /* buffer B status (not A) */ 434 #define TIS_TXEMPTY 0x02 /* transmitter empty */ 435 #define TIS_TXDATA 0x01 /* transmit data below threshold */ 436 #define TIS_BITS "\20\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr" 437 438 /* 439 * Local interrupt vector register (LIVR) bits. 440 */ 441 #define LIV_EXCEP 0 442 #define LIV_MODEM 1 443 #define LIV_TXDATA 2 444 #define LIV_RXDATA 3 445 446 /* 447 * Transmit end of interrupt registers (TEOIR) bits. 448 */ 449 #define TEOI_TERMBUFF 0x80 /* force current buffer to be discarded */ 450 #define TEOI_EOFR 0x40 /* end of frame in interrupt mode */ 451 #define TEOI_SETTM2 0x20 /* set general timer 2 in sync mode */ 452 #define TEOI_SETTM1 0x10 /* set general timer 1 in sync mode */ 453 #define TEOI_NOTRANSF 0x08 /* no transfer of data on this interrupt */ 454 455 /* 456 * Receive end of interrupt registers (REOIR) bits. 457 */ 458 #define REOI_TERMBUFF 0x80 /* force current buffer to be terminated */ 459 #define REOI_DISCEXC 0x40 /* discard exception character */ 460 #define REOI_SETTM2 0x20 /* set general timer 2 */ 461 #define REOI_SETTM1 0x10 /* set general timer 1 */ 462 #define REOI_NOTRANSF 0x08 /* no transfer of data */ 463 #define REOI_GAP_MASK 0x07 /* optional gap size to leave in buffer */ 464 465 /* 466 * Special transmit command register (STCR) bits. 467 */ 468 #define STC_ABORTTX 0x40 /* abort transmission (HDLC mode) */ 469 #define STC_APPDCMP 0x20 /* append complete (async DMA mode) */ 470 #define STC_SNDSPC 0x08 /* send special characters (async mode) */ 471 #define STC_SSPC_MASK 0x07 /* special character select */ 472 #define STC_SSPC_1 0x01 /* send special character #1 */ 473 #define STC_SSPC_2 0x02 /* send special character #2 */ 474 #define STC_SSPC_3 0x03 /* send special character #3 */ 475 #define STC_SSPC_4 0x04 /* send special character #4 */ 476 477 /* 478 * Channel status register (CSR) bits, asynchronous mode. 479 */ 480 #define CSRA_RXEN 0x80 /* receiver enable */ 481 #define CSRA_RXFLOFF 0x40 /* receiver flow off */ 482 #define CSRA_RXFLON 0x20 /* receiver flow on */ 483 #define CSRA_TXEN 0x08 /* transmitter enable */ 484 #define CSRA_TXFLOFF 0x04 /* transmitter flow off */ 485 #define CSRA_TXFLON 0x02 /* transmitter flow on */ 486 #define CSRA_BITS "\20\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen" 487