1 /*- 2 * Copyright (c) 2009 Greg Ansley All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * $FreeBSD$ 28 */ 29 30 #ifndef _AT91REG_H_ 31 #define _AT91REG_H_ 32 33 #include "opt_at91.h" 34 35 /* Where builtin peripherals start in KVM */ 36 #define AT91_BASE 0xd0000000 37 38 /* Where builtin peripherals start PA */ 39 #define AT91_PA_BASE 0xf0000000 40 41 /* A few things that we count on being the same 42 * throught the whole family of SOCs */ 43 44 /* SYSC System Controler */ 45 /* System Registers */ 46 #define AT91_SYS_BASE 0xffff000 47 #define AT91_SYS_SIZE 0x1000 48 49 #define AT91_DBGU0 0x0ffff200 /* Most */ 50 #define AT91_DBGU1 0x0fffee00 /* SAM9263, CAP9, and SAM9G45 */ 51 52 #define AT91_DBGU_SIZE 0x200 53 #define DBGU_C1R (64) /* Chip ID1 Register */ 54 #define DBGU_C2R (68) /* Chip ID2 Register */ 55 #define DBGU_FNTR (72) /* Force NTRST Register */ 56 57 #define AT91_CPU_VERSION_MASK 0x0000001f 58 #define AT91_CPU_FAMILY_MASK 0x0ff00000 59 60 #define AT91_CPU_RM9200 0x09290780 61 #define AT91_CPU_SAM9260 0x019803a0 62 #define AT91_CPU_SAM9261 0x019703a0 63 #define AT91_CPU_SAM9263 0x019607a0 64 #define AT91_CPU_SAM9G10 0x819903a0 65 #define AT91_CPU_SAM9G20 0x019905a0 66 #define AT91_CPU_SAM9G45 0x819b05a0 67 #define AT91_CPU_SAM9N12 0x819a07a0 68 #define AT91_CPU_SAM9RL64 0x019b03a0 69 #define AT91_CPU_SAM9X5 0x819a05a0 70 71 #define AT91_CPU_SAM9XE128 0x329973a0 72 #define AT91_CPU_SAM9XE256 0x329a93a0 73 #define AT91_CPU_SAM9XE512 0x329aa3a0 74 75 #define AT91_CPU_CAP9 0x039a03a0 76 77 #define AT91_EXID_SAM9M11 0x00000001 78 #define AT91_EXID_SAM9M10 0x00000002 79 #define AT91_EXID_SAM9G46 0x00000003 80 #define AT91_EXID_SAM9G45 0x00000004 81 82 #define AT91_EXID_SAM9G15 0x00000000 83 #define AT91_EXID_SAM9G35 0x00000001 84 #define AT91_EXID_SAM9X35 0x00000002 85 #define AT91_EXID_SAM9G25 0x00000003 86 #define AT91_EXID_SAM9X25 0x00000004 87 88 #define AT91_IRQ_SYSTEM 1 89 90 #endif /* _AT91REG_H_ */ 91