1 /* $NetBSD: ast_drv.h,v 1.3 2021/12/18 23:45:27 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27 /*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30 #ifndef __AST_DRV_H__
31 #define __AST_DRV_H__
32
33 #include <linux/types.h>
34 #include <linux/io.h>
35 #include <linux/i2c.h>
36 #include <linux/i2c-algo-bit.h>
37
38 #include <drm/drm_connector.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_encoder.h>
41 #include <drm/drm_mode.h>
42 #include <drm/drm_framebuffer.h>
43 #include <drm/drm_fb_helper.h>
44
45 #define DRIVER_AUTHOR "Dave Airlie"
46
47 #define DRIVER_NAME "ast"
48 #define DRIVER_DESC "AST"
49 #define DRIVER_DATE "20120228"
50
51 #define DRIVER_MAJOR 0
52 #define DRIVER_MINOR 1
53 #define DRIVER_PATCHLEVEL 0
54
55 #define PCI_CHIP_AST2000 0x2000
56 #define PCI_CHIP_AST2100 0x2010
57 #define PCI_CHIP_AST1180 0x1180
58
59
60 enum ast_chip {
61 AST2000,
62 AST2100,
63 AST1100,
64 AST2200,
65 AST2150,
66 AST2300,
67 AST2400,
68 AST2500,
69 AST1180,
70 };
71
72 enum ast_tx_chip {
73 AST_TX_NONE,
74 AST_TX_SIL164,
75 AST_TX_ITE66121,
76 AST_TX_DP501,
77 };
78
79 #define AST_DRAM_512Mx16 0
80 #define AST_DRAM_1Gx16 1
81 #define AST_DRAM_512Mx32 2
82 #define AST_DRAM_1Gx32 3
83 #define AST_DRAM_2Gx16 6
84 #define AST_DRAM_4Gx16 7
85 #define AST_DRAM_8Gx16 8
86
87
88 #define AST_MAX_HWC_WIDTH 64
89 #define AST_MAX_HWC_HEIGHT 64
90
91 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
92 #define AST_HWC_SIGNATURE_SIZE 32
93
94 #define AST_DEFAULT_HWC_NUM 2
95
96 /* define for signature structure */
97 #define AST_HWC_SIGNATURE_CHECKSUM 0x00
98 #define AST_HWC_SIGNATURE_SizeX 0x04
99 #define AST_HWC_SIGNATURE_SizeY 0x08
100 #define AST_HWC_SIGNATURE_X 0x0C
101 #define AST_HWC_SIGNATURE_Y 0x10
102 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
103 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
104
105
106 struct ast_private {
107 struct drm_device *dev;
108
109 void __iomem *regs;
110 void __iomem *ioregs;
111
112 enum ast_chip chip;
113 bool vga2_clone;
114 uint32_t dram_bus_width;
115 uint32_t dram_type;
116 uint32_t mclk;
117 uint32_t vram_size;
118
119 int fb_mtrr;
120
121 struct {
122 struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM];
123 unsigned int next_index;
124 } cursor;
125
126 struct drm_plane primary_plane;
127 struct drm_plane cursor_plane;
128
129 bool support_wide_screen;
130 enum {
131 ast_use_p2a,
132 ast_use_dt,
133 ast_use_defaults
134 } config_mode;
135
136 enum ast_tx_chip tx_chip_type;
137 u8 dp501_maxclk;
138 u8 *dp501_fw_addr;
139 const struct firmware *dp501_fw; /* dp501 fw */
140 };
141
142 int ast_driver_load(struct drm_device *dev, unsigned long flags);
143 void ast_driver_unload(struct drm_device *dev);
144
145 #define AST_IO_AR_PORT_WRITE (0x40)
146 #define AST_IO_MISC_PORT_WRITE (0x42)
147 #define AST_IO_VGA_ENABLE_PORT (0x43)
148 #define AST_IO_SEQ_PORT (0x44)
149 #define AST_IO_DAC_INDEX_READ (0x47)
150 #define AST_IO_DAC_INDEX_WRITE (0x48)
151 #define AST_IO_DAC_DATA (0x49)
152 #define AST_IO_GR_PORT (0x4E)
153 #define AST_IO_CRTC_PORT (0x54)
154 #define AST_IO_INPUT_STATUS1_READ (0x5A)
155 #define AST_IO_MISC_PORT_READ (0x4C)
156
157 #define AST_IO_MM_OFFSET (0x380)
158
159 #define __ast_read(x) \
160 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
161 u##x val = 0;\
162 val = ioread##x(ast->regs + reg); \
163 return val;\
164 }
165
166 __ast_read(8);
167 __ast_read(16);
168 __ast_read(32)
169
170 #define __ast_io_read(x) \
171 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
172 u##x val = 0;\
173 val = ioread##x(ast->ioregs + reg); \
174 return val;\
175 }
176
177 __ast_io_read(8);
178 __ast_io_read(16);
179 __ast_io_read(32);
180
181 #define __ast_write(x) \
182 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
183 iowrite##x(val, ast->regs + reg);\
184 }
185
186 __ast_write(8);
187 __ast_write(16);
188 __ast_write(32);
189
190 #define __ast_io_write(x) \
191 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
192 iowrite##x(val, ast->ioregs + reg);\
193 }
194
195 __ast_io_write(8);
196 __ast_io_write(16);
197 #undef __ast_io_write
198
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)199 static inline void ast_set_index_reg(struct ast_private *ast,
200 uint32_t base, uint8_t index,
201 uint8_t val)
202 {
203 ast_io_write16(ast, base, ((u16)val << 8) | index);
204 }
205
206 void ast_set_index_reg_mask(struct ast_private *ast,
207 uint32_t base, uint8_t index,
208 uint8_t mask, uint8_t val);
209 uint8_t ast_get_index_reg(struct ast_private *ast,
210 uint32_t base, uint8_t index);
211 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
212 uint32_t base, uint8_t index, uint8_t mask);
213
ast_open_key(struct ast_private * ast)214 static inline void ast_open_key(struct ast_private *ast)
215 {
216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
217 }
218
219 #define AST_VIDMEM_SIZE_8M 0x00800000
220 #define AST_VIDMEM_SIZE_16M 0x01000000
221 #define AST_VIDMEM_SIZE_32M 0x02000000
222 #define AST_VIDMEM_SIZE_64M 0x04000000
223 #define AST_VIDMEM_SIZE_128M 0x08000000
224
225 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
226
227 struct ast_i2c_chan {
228 struct i2c_adapter adapter;
229 struct drm_device *dev;
230 struct i2c_algo_bit_data bit;
231 };
232
233 struct ast_connector {
234 struct drm_connector base;
235 struct ast_i2c_chan *i2c;
236 };
237
238 struct ast_crtc {
239 struct drm_crtc base;
240 u8 offset_x, offset_y;
241 };
242
243 struct ast_encoder {
244 struct drm_encoder base;
245 };
246
247 #define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
248 #define to_ast_connector(x) container_of(x, struct ast_connector, base)
249 #define to_ast_encoder(x) container_of(x, struct ast_encoder, base)
250
251 struct ast_vbios_stdtable {
252 u8 misc;
253 u8 seq[4];
254 u8 crtc[25];
255 u8 ar[20];
256 u8 gr[9];
257 };
258
259 struct ast_vbios_enhtable {
260 u32 ht;
261 u32 hde;
262 u32 hfp;
263 u32 hsync;
264 u32 vt;
265 u32 vde;
266 u32 vfp;
267 u32 vsync;
268 u32 dclk_index;
269 u32 flags;
270 u32 refresh_rate;
271 u32 refresh_rate_index;
272 u32 mode_id;
273 };
274
275 struct ast_vbios_dclk_info {
276 u8 param1;
277 u8 param2;
278 u8 param3;
279 };
280
281 struct ast_vbios_mode_info {
282 const struct ast_vbios_stdtable *std_table;
283 const struct ast_vbios_enhtable *enh_table;
284 };
285
286 struct ast_crtc_state {
287 struct drm_crtc_state base;
288
289 /* Last known format of primary plane */
290 const struct drm_format_info *format;
291
292 struct ast_vbios_mode_info vbios_mode_info;
293 };
294
295 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
296
297 extern int ast_mode_init(struct drm_device *dev);
298 extern void ast_mode_fini(struct drm_device *dev);
299
300 #define AST_MM_ALIGN_SHIFT 4
301 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
302
303 int ast_mm_init(struct ast_private *ast);
304 void ast_mm_fini(struct ast_private *ast);
305
306 /* ast post */
307 void ast_enable_vga(struct drm_device *dev);
308 void ast_enable_mmio(struct drm_device *dev);
309 bool ast_is_vga_enabled(struct drm_device *dev);
310 void ast_post_gpu(struct drm_device *dev);
311 u32 ast_mindwm(struct ast_private *ast, u32 r);
312 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
313 /* ast dp501 */
314 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
315 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
316 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
317 u8 ast_get_dp501_max_clk(struct drm_device *dev);
318 void ast_init_3rdtx(struct drm_device *dev);
319 void ast_release_firmware(struct drm_device *dev);
320 #endif
321