1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #ifndef _DEV_ATH_AR5212PHY_H_ 20 #define _DEV_ATH_AR5212PHY_H_ 21 22 /* PHY registers */ 23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */ 24 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 25 26 #define AR_PHY_TEST 0x9800 /* PHY test control */ 27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ 28 29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */ 30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */ 31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */ 32 #define AR_PHY_TESTCTRL_TXSRC_ALT_S 7 33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */ 34 #define AR_PHY_TESTCTRL_TXSRC_SRC_S 1 35 36 #define AR_PHY_TURBO 0x9804 /* frame control register */ 37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */ 38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 39 #define AR_PHY_FC_TURBO_MIMO 0x00000004 /* Set turbo for mimo mode */ 40 41 #define AR_PHY_TIMING3 0x9814 /* Timing control 3 */ 42 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 43 #define AR_PHY_TIMING3_DSC_MAN_S 17 44 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 45 #define AR_PHY_TIMING3_DSC_EXP_S 13 46 47 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ 48 #define AR_PHY_CHIP_ID_REV_2 0x42 /* 5212 Rev 2 BB w. TPC fix */ 49 #define AR_PHY_CHIP_ID_REV_3 0x43 /* 5212 Rev 3 5213 */ 50 #define AR_PHY_CHIP_ID_REV_4 0x44 /* 5212 Rev 4 2313 and up */ 51 52 #define AR_PHY_ACTIVE 0x981C /* activation register */ 53 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ 54 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ 55 56 #define AR_PHY_TX_CTL 0x9824 57 #define AR_PHY_TX_FRAME_TO_TX_DATA_START 0x0000000f 58 #define AR_PHY_TX_FRAME_TO_TX_DATA_START_S 0 59 60 #define AR_PHY_ADC_CTL 0x982C 61 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 62 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 63 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 64 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */ 65 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */ 66 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 67 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 68 69 #define AR_PHY_BB_XP_PA_CTL 0x9838 70 #define AR_PHY_BB_XPAA_ACTIVE_HIGH 0x00000001 71 #define AR_PHY_BB_XPAB_ACTIVE_HIGH 0x00000002 72 #define AR_PHY_BB_XPAB_ACTIVE_HIGH_S 1 73 74 #define AR_PHY_TSTDAC_CONST 0x983C 75 #define AR_PHY_TSTDAC_CONST_Q 0x0003FE00 76 #define AR_PHY_TSTDAC_CONST_Q_S 9 77 #define AR_PHY_TSTDAC_CONST_I 0x000001FF 78 79 80 #define AR_PHY_SETTLING 0x9844 81 #define AR_PHY_SETTLING_AGC 0x0000007F 82 #define AR_PHY_SETTLING_AGC_S 0 83 #define AR_PHY_SETTLING_SWITCH 0x00003F80 84 #define AR_PHY_SETTLING_SWITCH_S 7 85 86 #define AR_PHY_RXGAIN 0x9848 87 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 88 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 89 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 90 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 91 92 #define AR_PHY_DESIRED_SZ 0x9850 93 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 94 #define AR_PHY_DESIRED_SZ_ADC_S 0 95 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 96 #define AR_PHY_DESIRED_SZ_PGA_S 8 97 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 98 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 99 100 #define AR_PHY_FIND_SIG 0x9858 101 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 102 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 103 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 104 #define AR_PHY_FIND_SIG_FIRPWR_S 18 105 106 #define AR_PHY_AGC_CTL1 0x985C 107 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 108 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 109 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 110 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 111 112 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */ 113 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 114 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */ 115 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* Enable noise floor calibration to happen */ 116 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* Allow Filter calibration */ 117 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* Don't update noise floor automatically */ 118 119 #define AR_PHY_SFCORR_LOW 0x986C 120 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 121 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 122 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 123 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 124 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 125 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 126 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 127 128 #define AR_PHY_SFCORR 0x9868 129 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 130 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 131 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 132 #define AR_PHY_SFCORR_M1_THRESH_S 17 133 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 134 #define AR_PHY_SFCORR_M2_THRESH_S 24 135 136 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 137 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 138 #define AR_PHY_SLEEP_SCAL 0x9878 139 140 #define AR_PHY_PLL_CTL 0x987c /* PLL control register */ 141 #define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */ 142 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ 143 #define AR_PHY_PLL_CTL_44_5112 0xeb /* 44 MHz for 11b, 11g */ 144 #define AR_PHY_PLL_CTL_40_5112 0xea /* 40 MHz for 11a, turbos */ 145 #define AR_PHY_PLL_CTL_40_5413 0x04 /* 40 MHz for 11a, turbos with 5413 */ 146 #define AR_PHY_PLL_CTL_HALF 0x100 /* Half clock for 1/2 chan width */ 147 #define AR_PHY_PLL_CTL_QUARTER 0x200 /* Quarter clock for 1/4 chan width */ 148 149 #define AR_PHY_BIN_MASK_1 0x9900 150 #define AR_PHY_BIN_MASK_2 0x9904 151 #define AR_PHY_BIN_MASK_3 0x9908 152 153 #define AR_PHY_MASK_CTL 0x990c /* What are these for?? */ 154 #define AR_PHY_MASK_CTL_MASK_4 0x00003FFF 155 #define AR_PHY_MASK_CTL_MASK_4_S 0 156 #define AR_PHY_MASK_CTL_RATE 0xFF000000 157 #define AR_PHY_MASK_CTL_RATE_S 24 158 159 #define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */ 160 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 161 162 #define AR_PHY_TIMING_CTRL4 0x9920 /* timing control */ 163 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ 164 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 165 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ 166 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 167 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ 168 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 169 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 170 #define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */ 171 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */ 172 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 173 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 174 175 #define AR_PHY_TIMING5 0x9924 176 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 177 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 178 179 #define AR_PHY_PAPD_PROBE 0x9930 180 #define AR_PHY_PAPD_PROBE_POWERTX 0x00007E00 181 #define AR_PHY_PAPD_PROBE_POWERTX_S 9 182 #define AR_PHY_PAPD_PROBE_NEXT_TX 0x00008000 /* command to take next reading */ 183 #define AR_PHY_PAPD_PROBE_TYPE 0x01800000 184 #define AR_PHY_PAPD_PROBE_TYPE_S 23 185 #define AR_PHY_PAPD_PROBE_TYPE_OFDM 0 186 #define AR_PHY_PAPD_PROBE_TYPE_CCK 2 187 #define AR_PHY_PAPD_PROBE_GAINF 0xFE000000 188 #define AR_PHY_PAPD_PROBE_GAINF_S 25 189 190 #define AR_PHY_POWER_TX_RATE1 0x9934 191 #define AR_PHY_POWER_TX_RATE2 0x9938 192 #define AR_PHY_POWER_TX_RATE_MAX 0x993c 193 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 194 195 #define AR_PHY_FRAME_CTL 0x9944 196 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 197 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 198 #define AR_PHY_FRAME_CTL_ERR_SERV 0x20000000 199 #define AR_PHY_FRAME_CTL_ERR_SERV_S 29 200 #define AR_PHY_FRAME_CTL_EMU_M 0x80000000 201 #define AR_PHY_FRAME_CTL_EMU_S 31 202 #define AR_PHY_FRAME_CTL_WINLEN 0x00000003 203 #define AR_PHY_FRAME_CTL_WINLEN_S 0 204 205 #define AR_PHY_TXPWRADJ 0x994C /* BB Rev 4.2+ only */ 206 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 207 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 208 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 209 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 210 211 #define AR_PHY_RADAR_0 0x9954 /* radar detection settings */ 212 #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ 213 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ 214 #define AR_PHY_RADAR_0_INBAND_S 1 215 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ 216 #define AR_PHY_RADAR_0_PRSSI_S 6 217 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ 218 #define AR_PHY_RADAR_0_HEIGHT_S 12 219 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ 220 #define AR_PHY_RADAR_0_RRSSI_S 18 221 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ 222 #define AR_PHY_RADAR_0_FIRPWR_S 24 223 224 /* ar5413 specific */ 225 #define AR_PHY_RADAR_2 0x9958 /* radar detection settings */ 226 #define AR_PHY_RADAR_2_ENRELSTEPCHK 0x00002000 /* Enable using max rssi */ 227 #define AR_PHY_RADAR_2_ENMAXRSSI 0x00004000 /* Enable using max rssi */ 228 #define AR_PHY_RADAR_2_BLOCKOFDMWEAK 0x00008000 /* En block OFDM weak sig as radar */ 229 #define AR_PHY_RADAR_2_USEFIR128 0x00400000 /* En measuring pwr over 128 cycles */ 230 #define AR_PHY_RADAR_2_ENRELPWRCHK 0x00800000 /* Enable using max rssi */ 231 #define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */ 232 #define AR_PHY_RADAR_2_MAXLEN_S 0 233 #define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */ 234 #define AR_PHY_RADAR_2_RELSTEP_S 8 235 #define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */ 236 #define AR_PHY_RADAR_2_RELPWR_S 16 237 238 #define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */ 239 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 240 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 241 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 242 #define AR_PHY_SIGMA_DELTA_FILT2_S 3 243 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 244 #define AR_PHY_SIGMA_DELTA_FILT1_S 8 245 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 246 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 247 248 #define AR_PHY_RESTART 0x9970 /* restart */ 249 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 250 #define AR_PHY_RESTART_DIV_GC_S 18 251 252 #define AR_PHY_RFBUS_REQ 0x997C 253 #define AR_PHY_RFBUS_REQ_REQUEST 0x00000001 254 255 #define AR_PHY_TIMING7 0x9980 /* Spur mitigation masks */ 256 #define AR_PHY_TIMING8 0x9984 257 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 258 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 259 260 #define AR_PHY_BIN_MASK2_1 0x9988 261 #define AR_PHY_BIN_MASK2_2 0x998c 262 #define AR_PHY_BIN_MASK2_3 0x9990 263 #define AR_PHY_BIN_MASK2_4 0x9994 264 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 265 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 266 267 #define AR_PHY_TIMING9 0x9998 268 #define AR_PHY_TIMING10 0x999c 269 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 270 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 271 272 #define AR_PHY_TIMING11 0x99a0 /* Spur Mitigation control */ 273 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 274 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 275 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 276 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 277 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 278 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 279 280 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 281 282 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 283 #define AR_PHY_REFCLKDLY 0x99f4 284 #define AR_PHY_REFCLKPD 0x99f8 285 286 /* PHY IQ calibration results */ 287 #define AR_PHY_IQCAL_RES_PWR_MEAS_I 0x9c10 /* power measurement for I */ 288 #define AR_PHY_IQCAL_RES_PWR_MEAS_Q 0x9c14 /* power measurement for Q */ 289 #define AR_PHY_IQCAL_RES_IQ_CORR_MEAS 0x9c18 /* IQ correlation measurement */ 290 291 #define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame rx'd */ 292 293 #define AR_PHY_RFBUS_GNT 0x9c20 294 #define AR_PHY_RFBUS_GNT_GRANT 0x1 295 296 #define AR_PHY_PCDAC_TX_POWER_0 0xA180 297 #define AR_PHY_PCDAC_TX_POWER(_n) (AR_PHY_PCDAC_TX_POWER_0 + ((_n)<<2)) 298 299 #define AR_PHY_MODE 0xA200 /* Mode register */ 300 #define AR_PHY_MODE_QUARTER 0x40 /* Quarter Rate */ 301 #define AR_PHY_MODE_HALF 0x20 /* Half Rate */ 302 #define AR_PHY_MODE_AR5112 0x08 /* AR5112 */ 303 #define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */ 304 #define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */ 305 #define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */ 306 #define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */ 307 #define AR_PHY_MODE_CCK 0x01 /* CCK */ 308 #define AR_PHY_MODE_OFDM 0x00 /* OFDM */ 309 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 /* Disable dynamic CCK detection */ 310 311 #define AR_PHY_CCK_TX_CTRL 0xA204 312 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 313 314 #define AR_PHY_CCK_DETECT 0xA208 315 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 316 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 317 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 318 319 #define AR_PHY_GAIN_2GHZ 0xA20C 320 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 321 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 322 323 #define AR_PHY_CCK_RXCTRL4 0xA21C 324 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 325 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 326 327 #define AR_PHY_DAG_CTRLCCK 0xA228 328 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */ 329 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */ 330 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB Rev 4.2+ only */ 331 332 #define AR_PHY_POWER_TX_RATE3 0xA234 333 #define AR_PHY_POWER_TX_RATE4 0xA238 334 335 #define AR_PHY_FAST_ADC 0xA24C 336 #define AR_PHY_BLUETOOTH 0xA254 337 338 #define AR_PHY_TPCRG1 0xA258 /* ar2413 power control */ 339 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 340 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 341 #define AR_PHY_TPCRG1_PDGAIN_SETTING1 0x00030000 342 #define AR_PHY_TPCRG1_PDGAIN_SETTING1_S 16 343 #define AR_PHY_TPCRG1_PDGAIN_SETTING2 0x000c0000 344 #define AR_PHY_TPCRG1_PDGAIN_SETTING2_S 18 345 #define AR_PHY_TPCRG1_PDGAIN_SETTING3 0x00300000 346 #define AR_PHY_TPCRG1_PDGAIN_SETTING3_S 20 347 348 #define AR_PHY_TPCRG5 0xA26C /* ar2413 power control */ 349 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 350 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 351 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 352 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 353 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 354 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 355 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 356 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 357 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 358 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 359 360 #endif /* _DEV_ATH_AR5212PHY_H_ */ 361