1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5212desc.h,v 1.1.1.1 2008/12/11 04:46:43 alc Exp $ 18 */ 19 #ifndef _ATH_AR5212_DESC_H_ 20 #define _ATH_AR5212_DESC_H_ 21 22 /* 23 * Hardware-specific descriptor structures. 24 */ 25 #include "ah_desc.h" 26 27 /* 28 * AR5212-specific tx/rx descriptor definition. 29 */ 30 struct ar5212_desc { 31 uint32_t ds_link; /* link pointer */ 32 uint32_t ds_data; /* data buffer pointer */ 33 uint32_t ds_ctl0; /* DMA control 0 */ 34 uint32_t ds_ctl1; /* DMA control 1 */ 35 union { 36 struct { /* xmit format */ 37 uint32_t ctl2; /* DMA control 2 */ 38 uint32_t ctl3; /* DMA control 3 */ 39 uint32_t status0;/* DMA status 0 */ 40 uint32_t status1;/* DMA status 1 */ 41 } tx; 42 struct { /* recv format */ 43 uint32_t status0;/* DMA status 0 */ 44 uint32_t status1;/* DMA status 1 */ 45 } rx; 46 } u; 47 } __packed; 48 #define AR5212DESC(_ds) ((struct ar5212_desc *)(_ds)) 49 #define AR5212DESC_CONST(_ds) ((const struct ar5212_desc *)(_ds)) 50 51 #define ds_ctl2 u.tx.ctl2 52 #define ds_ctl3 u.tx.ctl3 53 #define ds_txstatus0 u.tx.status0 54 #define ds_txstatus1 u.tx.status1 55 #define ds_rxstatus0 u.rx.status0 56 #define ds_rxstatus1 u.rx.status1 57 58 /* TX ds_ctl0 */ 59 #define AR_FrameLen 0x00000fff /* frame length */ 60 /* bits 12-15 are reserved */ 61 #define AR_XmitPower 0x003f0000 /* transmit power control */ 62 #define AR_XmitPower_S 16 63 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */ 64 #define AR_VEOL 0x00800000 /* virtual end-of-list */ 65 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */ 66 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */ 67 #define AR_AntModeXmit_S 25 68 #define AR_TxInterReq 0x20000000 /* TX interrupt request */ 69 #define AR_DestIdxValid 0x40000000 /* destination index valid */ 70 #define AR_CTSEnable 0x80000000 /* precede frame with CTS */ 71 72 /* TX ds_ctl1 */ 73 #define AR_BufLen 0x00000fff /* data buffer length */ 74 #define AR_More 0x00001000 /* more desc in this frame */ 75 #define AR_DestIdx 0x000fe000 /* destination table index */ 76 #define AR_DestIdx_S 13 77 #define AR_FrmType 0x00f00000 /* frame type indication */ 78 #define AR_FrmType_S 20 79 #define AR_NoAck 0x01000000 /* No ACK flag */ 80 #define AR_CompProc 0x06000000 /* compression processing */ 81 #define AR_CompProc_S 25 82 #define AR_CompIVLen 0x18000000 /* length of frame IV */ 83 #define AR_CompIVLen_S 27 84 #define AR_CompICVLen 0x60000000 /* length of frame ICV */ 85 #define AR_CompICVLen_S 29 86 /* bit 31 is reserved */ 87 88 /* TX ds_ctl2 */ 89 #define AR_RTSCTSDuration 0x00007fff /* RTS/CTS duration */ 90 #define AR_RTSCTSDuration_S 0 91 #define AR_DurUpdateEna 0x00008000 /* frame duration update ctl */ 92 #define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */ 93 #define AR_XmitDataTries0_S 16 94 #define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */ 95 #define AR_XmitDataTries1_S 20 96 #define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */ 97 #define AR_XmitDataTries2_S 24 98 #define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */ 99 #define AR_XmitDataTries3_S 28 100 101 /* TX ds_ctl3 */ 102 #define AR_XmitRate0 0x0000001f /* series 0 tx rate */ 103 #define AR_XmitRate0_S 0 104 #define AR_XmitRate1 0x000003e0 /* series 1 tx rate */ 105 #define AR_XmitRate1_S 5 106 #define AR_XmitRate2 0x00007c00 /* series 2 tx rate */ 107 #define AR_XmitRate2_S 10 108 #define AR_XmitRate3 0x000f8000 /* series 3 tx rate */ 109 #define AR_XmitRate3_S 15 110 #define AR_RTSCTSRate 0x01f00000 /* RTS or CTS rate */ 111 #define AR_RTSCTSRate_S 20 112 /* bits 25-31 are reserved */ 113 114 /* RX ds_ctl1 */ 115 /* AR_BufLen 0x00000fff data buffer length */ 116 /* bit 12 is reserved */ 117 #define AR_RxInterReq 0x00002000 /* RX interrupt request */ 118 /* bits 14-31 are reserved */ 119 120 /* TX ds_txstatus0 */ 121 #define AR_FrmXmitOK 0x00000001 /* TX success */ 122 #define AR_ExcessiveRetries 0x00000002 /* excessive retries */ 123 #define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */ 124 #define AR_Filtered 0x00000008 /* TX filter indication */ 125 #define AR_RTSFailCnt 0x000000f0 /* RTS failure count */ 126 #define AR_RTSFailCnt_S 4 127 #define AR_DataFailCnt 0x00000f00 /* Data failure count */ 128 #define AR_DataFailCnt_S 8 129 #define AR_VirtCollCnt 0x0000f000 /* virtual collision count */ 130 #define AR_VirtCollCnt_S 12 131 #define AR_SendTimestamp 0xffff0000 /* TX timestamp */ 132 #define AR_SendTimestamp_S 16 133 134 /* RX ds_rxstatus0 */ 135 #define AR_DataLen 0x00000fff /* RX data length */ 136 /* AR_More 0x00001000 more desc in this frame */ 137 #define AR_DecompCRCErr 0x00002000 /* decompression CRC error */ 138 /* bit 14 is reserved */ 139 #define AR_RcvRate 0x000f8000 /* reception rate */ 140 #define AR_RcvRate_S 15 141 #define AR_RcvSigStrength 0x0ff00000 /* receive signal strength */ 142 #define AR_RcvSigStrength_S 20 143 #define AR_RcvAntenna 0xf0000000 /* receive antenaa */ 144 #define AR_RcvAntenna_S 28 145 146 /* TX ds_txstatus1 */ 147 #define AR_Done 0x00000001 /* descripter complete */ 148 #define AR_SeqNum 0x00001ffe /* TX sequence number */ 149 #define AR_SeqNum_S 1 150 #define AR_AckSigStrength 0x001fe000 /* strength of ACK */ 151 #define AR_AckSigStrength_S 13 152 #define AR_FinalTSIndex 0x00600000 /* final TX attempt series ix */ 153 #define AR_FinalTSIndex_S 21 154 #define AR_CompSuccess 0x00800000 /* compression status */ 155 #define AR_XmitAtenna 0x01000000 /* transmit antenna */ 156 /* bits 25-31 are reserved */ 157 158 /* RX ds_rxstatus1 */ 159 /* AR_Done 0x00000001 descripter complete */ 160 #define AR_FrmRcvOK 0x00000002 /* frame reception success */ 161 #define AR_CRCErr 0x00000004 /* CRC error */ 162 #define AR_DecryptCRCErr 0x00000008 /* Decryption CRC fiailure */ 163 #define AR_PHYErr 0x00000010 /* PHY error */ 164 #define AR_MichaelErr 0x00000020 /* Michae MIC decrypt error */ 165 /* bits 6-7 are reserved */ 166 #define AR_KeyIdxValid 0x00000100 /* decryption key index valid */ 167 #define AR_KeyIdx 0x0000fe00 /* Decryption key index */ 168 #define AR_KeyIdx_S 9 169 #define AR_RcvTimestamp 0x7fff0000 /* timestamp */ 170 #define AR_RcvTimestamp_S 16 171 #define AR_KeyCacheMiss 0x80000000 /* key cache miss indication */ 172 173 /* NB: phy error code overlays key index and valid fields */ 174 #define AR_PHYErrCode 0x0000ff00 /* PHY error code */ 175 #define AR_PHYErrCode_S 8 176 177 #endif /* _ATH_AR5212_DESC_H_ */ 178