1 /* $NetBSD: bus_defs.h,v 1.3 2023/12/07 03:46:10 thorpej Exp $ */ 2 /* NetBSD: bus.h,v 1.27 2000/03/15 16:44:50 drochner Exp */ 3 /* $OpenBSD: bus.h,v 1.15 1999/08/11 23:15:21 niklas Exp $ */ 4 5 /*- 6 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 11 * NASA Ames Research Center. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1997 Per Fogelstrom. All rights reserved. 37 * Copyright (c) 1996 Niklas Hallqvist. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #ifndef _ARC_BUS_DEFS_H_ 67 #define _ARC_BUS_DEFS_H_ 68 #ifdef _KERNEL 69 70 #include <sys/vmem.h> 71 72 /* 73 * Bus address and size types 74 */ 75 typedef u_long bus_addr_t; 76 typedef u_long bus_size_t; 77 78 #define PRIxBUSADDR "lx" 79 #define PRIxBUSSIZE "lx" 80 #define PRIuBUSSIZE "lu" 81 82 #include <mips/locore.h> 83 84 #ifdef BUS_SPACE_DEBUG 85 #include <sys/systm.h> /* for printf() prototype */ 86 /* 87 * Macros for checking the aligned-ness of pointers passed to bus 88 * space ops. Strict alignment is required by the MIPS architecture, 89 * and a trap will occur if unaligned access is performed. These 90 * may aid in the debugging of a broken device driver by displaying 91 * useful information about the problem. 92 */ 93 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 94 ((((u_long)(p)) & (sizeof(t)-1)) == 0) 95 96 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 97 ({ \ 98 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 99 printf("%s 0x%lx not aligned to %d bytes %s:%d\n", \ 100 d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \ 101 } \ 102 (void) 0; \ 103 }) 104 105 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 106 #else 107 #define __BUS_SPACE_ADDRESS_SANITY(p,t,d) (void) 0 108 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 109 #endif /* BUS_SPACE_DEBUG */ 110 111 /* 112 * Access methods for bus resources and address space. 113 */ 114 typedef uint32_t bus_space_handle_t; 115 typedef struct arc_bus_space *bus_space_tag_t; 116 117 #define PRIxBSH "lx" 118 119 struct arc_bus_space { 120 const char *bs_name; 121 vmem_t *bs_arena; 122 bus_addr_t bs_start; 123 bus_size_t bs_size; 124 125 paddr_t bs_pbase; 126 vaddr_t bs_vbase; 127 128 /* sparse addressing shift count */ 129 uint8_t bs_stride_1; 130 uint8_t bs_stride_2; 131 uint8_t bs_stride_4; 132 uint8_t bs_stride_8; 133 134 /* compose a bus_space handle from tag/handle/addr/size/flags (MD) */ 135 int (*bs_compose_handle)(bus_space_tag_t, bus_addr_t, 136 bus_size_t, int, bus_space_handle_t *); 137 138 /* dispose a bus_space handle (MD) */ 139 int (*bs_dispose_handle)(bus_space_tag_t, bus_space_handle_t, 140 bus_size_t); 141 142 /* convert bus_space tag/handle to physical address (MD) */ 143 int (*bs_paddr)(bus_space_tag_t, bus_space_handle_t, 144 paddr_t *); 145 146 /* mapping/unmapping */ 147 int (*bs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int, 148 bus_space_handle_t *); 149 void (*bs_unmap)(bus_space_tag_t, bus_space_handle_t, bus_size_t); 150 int (*bs_subregion)(bus_space_tag_t, bus_space_handle_t, 151 bus_size_t, bus_size_t, bus_space_handle_t *); 152 paddr_t (*bs_mmap)(bus_space_tag_t, bus_addr_t, off_t, int, int); 153 154 /* allocation/deallocation */ 155 int (*bs_alloc)(bus_space_tag_t, bus_addr_t, bus_addr_t, 156 bus_size_t, bus_size_t, bus_size_t, int, 157 bus_addr_t *, bus_space_handle_t *); 158 void (*bs_free)(bus_space_tag_t, bus_space_handle_t, bus_size_t); 159 160 void *bs_aux; 161 }; 162 163 /* vaddr_t argument of arc_bus_space_init() */ 164 #define ARC_BUS_SPACE_UNMAPPED ((vaddr_t)0) 165 166 #define BUS_SPACE_MAP_CACHEABLE 0x01 167 #define BUS_SPACE_MAP_LINEAR 0x02 168 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 169 170 #define __BUS_SPACE_HAS_STREAM_METHODS 171 172 #define BUS_SPACE_BARRIER_READ 0x01 173 #define BUS_SPACE_BARRIER_WRITE 0x02 174 175 /* 176 * Flags used in various bus DMA methods. 177 */ 178 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 179 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 180 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 181 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 182 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 183 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 184 #define BUS_DMA_BUS2 0x020 185 #define BUS_DMA_BUS3 0x040 186 #define BUS_DMA_BUS4 0x080 187 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 188 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 189 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 190 191 #define ARC_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 192 193 /* Forwards needed by prototypes below. */ 194 struct mbuf; 195 struct uio; 196 197 /* 198 * Operations performed by bus_dmamap_sync(). 199 */ 200 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 201 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 202 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 203 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 204 205 typedef struct arc_bus_dma_tag *bus_dma_tag_t; 206 typedef struct arc_bus_dmamap *bus_dmamap_t; 207 208 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 209 210 /* 211 * bus_dma_segment_t 212 * 213 * Describes a single contiguous DMA transaction. Values 214 * are suitable for programming into DMA registers. 215 */ 216 struct arc_bus_dma_segment { 217 /* 218 * PUBLIC MEMBERS: these are used by device drivers. 219 */ 220 bus_addr_t ds_addr; /* DMA address */ 221 bus_size_t ds_len; /* length of transfer */ 222 /* 223 * PRIVATE MEMBERS for the DMA back-end.: not for use by drivers. 224 */ 225 vaddr_t _ds_paddr; /* CPU physical address */ 226 vaddr_t _ds_vaddr; /* virtual address, 0 if invalid */ 227 }; 228 typedef struct arc_bus_dma_segment bus_dma_segment_t; 229 230 /* 231 * bus_dma_tag_t 232 * 233 * A machine-dependent opaque type describing the implementation of 234 * DMA for a given bus. 235 */ 236 237 struct arc_bus_dma_tag { 238 bus_addr_t dma_offset; 239 240 /* 241 * DMA mapping methods. 242 */ 243 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 244 bus_size_t, bus_size_t, int, bus_dmamap_t *); 245 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 246 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 247 bus_size_t, struct proc *, int); 248 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 249 struct mbuf *, int); 250 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 251 struct uio *, int); 252 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 253 bus_dma_segment_t *, int, bus_size_t, int); 254 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 255 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 256 bus_addr_t, bus_size_t, int); 257 258 /* 259 * DMA memory utility functions. 260 */ 261 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 262 bus_size_t, bus_dma_segment_t *, int, int *, int); 263 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int); 264 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 265 int, size_t, void **, int); 266 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 267 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 268 int, off_t, int, int); 269 }; 270 271 /* 272 * bus_dmamap_t 273 * 274 * Describes a DMA mapping. 275 */ 276 struct arc_bus_dmamap { 277 /* 278 * PRIVATE MEMBERS: not for use by machine-independent code. 279 */ 280 bus_size_t _dm_size; /* largest DMA transfer mappable */ 281 int _dm_segcnt; /* number of segs this map can map */ 282 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 283 bus_size_t _dm_boundary; /* don't cross this */ 284 int _dm_flags; /* misc. flags */ 285 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 286 287 /* 288 * Private cookie to be used by the DMA back-end. 289 */ 290 void *_dm_cookie; 291 292 /* 293 * PUBLIC MEMBERS: these are used by machine-independent code. 294 */ 295 bus_size_t dm_maxsegsz; /* largest possible segment */ 296 bus_size_t dm_mapsize; /* size of the mapping */ 297 int dm_nsegs; /* # valid segments in mapping */ 298 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 299 }; 300 301 #endif /* _KERNEL */ 302 #endif /* _ARC_BUS_DEFS_H_ */ 303