1 /* $OpenBSD: tropicreg.h,v 1.2 2003/10/21 18:58:50 jmc Exp $ */ 2 /* $NetBSD: tropicreg.h,v 1.3 1999/10/17 23:53:45 cgd Exp $ */ 3 4 /* 5 * Mach Operating System 6 * Copyright (c) 1991 Carnegie Mellon University 7 * Copyright (c) 1991 IBM Corporation 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation, 15 * and that the name IBM not be used in advertising or publicity 16 * pertaining to distribution of the software without specific, written 17 * prior permission. 18 * 19 * CARNEGIE MELLON AND IBM ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS" 20 * CONDITION. CARNEGIE MELLON AND IBM DISCLAIM ANY LIABILITY OF ANY KIND FOR 21 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 22 * 23 * Carnegie Mellon requests users of this software to return to 24 * 25 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 26 * School of Computer Science 27 * Carnegie Mellon University 28 * Pittsburgh PA 15213-3890 29 * 30 * any improvements or extensions that they make and grant Carnegie Mellon 31 * the rights to redistribute these changes. 32 */ 33 34 /* $ACIS:if_lanreg.h 12.0$ */ 35 36 #define TR_SWITCH 0 37 #define TR_RESET 1 38 #define TR_RELEASE 2 39 #define TR_CLEARINT 3 40 41 /* macros to deal with accessing the MMIO region */ 42 #define MM_OUTB(sc, off, val) \ 43 bus_space_write_1((sc)->sc_memt, (sc)->sc_mmioh, (off), (val)) 44 #define MM_OUTW(sc, off, val) \ 45 bus_space_write_2((sc)->sc_memt, (sc)->sc_mmioh, (off), htons((val))) 46 #define MM_INB(sc, off) \ 47 bus_space_read_1((sc)->sc_memt, (sc)->sc_mmioh, (off)) 48 #define MM_INW(sc, off) \ 49 ntohs(bus_space_read_2((sc)->sc_memt, (sc)->sc_mmioh, (off))) 50 51 /* macros to deal with accesses to the shared ram */ 52 #define SR_INB(sc, off) \ 53 bus_space_read_1(sc->sc_memt, sc->sc_sramh, (off)) 54 #define SR_INW(sc, off) \ 55 htons(bus_space_read_2(sc->sc_memt, sc->sc_sramh, (off))) 56 #define SR_OUTB(sc, off, val) \ 57 bus_space_write_1((sc)->sc_memt, (sc)->sc_sramh, (off), (val)) 58 #define SR_OUTW(sc, off, val) \ 59 bus_space_write_2((sc)->sc_memt, (sc)->sc_sramh, (off), htons((val))) 60 61 /* macros to deal with accesses to the recv buffers */ 62 #define RB_INB(sc, rb, reg) SR_INB(sc, (rb)+(reg)) 63 #define RB_INW(sc, rb, reg) SR_INW(sc, (rb)+(reg)) 64 65 /* macros to deal with the ACA */ 66 #define ACA_RDB(sc, reg) MM_INB(sc, ((sc->sc_aca+(reg))|ACA_RW)) 67 #define ACA_RDW(sc, reg) MM_INW(sc, ((sc->sc_aca+(reg))|ACA_RW)) 68 #define ACA_OUTB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RW), (val)) 69 #define ACA_SETB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_SET), (val)) 70 #define ACA_RSTB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RST), (val)) 71 72 /* macros to deal with the SSB */ 73 #define SSB_INB(sc, ssb, reg) SR_INB(sc, (ssb)+(reg)) 74 75 /* macros to deal with the ARB */ 76 #define ARB_INB(sc, arb, reg) SR_INB(sc, (arb)+(reg)) 77 #define ARB_INW(sc, arb, reg) SR_INW(sc, (arb)+(reg)) 78 79 /* macros to deal with the SRB */ 80 #define SRB_INB(sc, srb, reg) SR_INB(sc, (srb)+(reg)) 81 #define SRB_INW(sc, srb, reg) SR_INW(sc, (srb)+(reg)) 82 #define SRB_OUTB(sc, srb, reg, val) SR_OUTB(sc, (srb)+(reg), (val)) 83 #define SRB_OUTW(sc, srb, reg, val) SR_OUTW(sc, (srb)+(reg), (val)) 84 85 /* macros to deal with the ASB */ 86 #define ASB_INB(sc, asb, reg) SR_INB(sc, (asb)+(reg)) 87 #define ASB_INW(sc, asb, reg) SR_INW(sc, (asb)+(reg)) 88 #define ASB_OUTB(sc, asb, reg, val) SR_OUTB(sc, (asb)+(reg), (val)) 89 #define ASB_OUTW(sc, asb, reg, val) SR_OUTW(sc, (asb)+(reg), (val)) 90 91 /* macros to deal with the TXCA */ 92 #define TXCA_INW(sc, reg) SR_INW(sc, sc->sc_txca+(reg)) 93 #define TXCA_OUTW(sc, reg, val) SR_OUTW(sc, sc->sc_txca+(reg), (val)) 94 95 /* macros to deal with the txbuffers */ 96 #define TXB_INB(sc, buf, reg) SR_INB(sc, (buf)+(reg)) 97 #define TXB_INW(sc, buf, reg) SR_INW(sc, (buf)+(reg)) 98 #define TXB_OUTB(sc, buf, reg, val) SR_OUTB(sc, (buf)+(reg), (val)) 99 #define TXB_OUTW(sc, buf, reg, val) SR_OUTW(sc, (buf)+(reg), (val)) 100 101 /* ACA registers */ 102 #define ACA_RRR 0 103 #define ACA_RRR_e ACA_RRR 104 #define ACA_RRR_o (ACA_RRR+1) 105 #define ACA_WRBR 2 106 #define ACA_WRBR_e ACA_WRBR 107 #define ACA_WRBR_o (ACA_WRBR+1) 108 #define ACA_WWOR 4 109 #define ACA_WWOR_e ACA_WWOR 110 #define ACA_WWOR_o (ACA_WWOR+1) 111 #define ACA_WWCR 6 112 #define ACA_WWCR_e ACA_WWCR 113 #define ACA_WWCR_o (ACA_WWCR+1) 114 #define ACA_ISRP 8 115 #define ACA_ISRP_e ACA_ISRP 116 #define ACA_ISRP_o (ACA_ISRP+1) 117 #define ACA_ISRA 10 118 #define ACA_ISRA_e ACA_ISRA 119 #define ACA_ISRA_o (ACA_ISRA+1) 120 #define ACA_TCR 12 121 #define ACA_TCR_e ACA_TCR 122 #define ACA_TCR_o (ACA_TCR+1) 123 #define ACA_TVR 14 124 #define ACA_TVR_e ACA_TVR 125 #define ACA_TVR_o (ACA_TVR+1) 126 127 /* access flags; to be or-ed into offset */ 128 #define ACA_RW 0 129 #define ACA_RST 0x20 130 #define ACA_SET 0x40 131 132 /* offsets valid for all command blocks */ 133 #define CMD_CMD 0 134 #define CMD_RETCODE 2 135 136 /* 137 * Structure of SSB (System Status Block) 138 */ 139 #define SSB_SIZE 20 /* size of SSB */ 140 #define SSB_CMD 0 141 #define SSB_CMDCORR 1 142 #define SSB_RETCODE 2 143 #define SSB_STATIONID 4 144 #define SSB_XMITERR 6 145 146 /* 147 * Structure of ARB (Adapter Request Block) 148 */ 149 #define ARB_SIZE 28 /* size of ARB */ 150 #define ARB_CMD 0 151 #define ARB_STATIONID 4 /* ID of receiving station */ 152 153 /* receive data command block */ 154 #define ARB_RXD_BUFADDR 6 /* RAM offset of 1st rec buf */ 155 #define ARB_RXD_LANHDRLEN 8 /* Length of LAN header */ 156 #define ARB_RXD_DLCHDRLEN 9 /* Length of DLC header */ 157 #define ARB_RXD_FRAMELEN 10 /* Length of entire frame */ 158 #define ARB_RXD_MSGTYPE 12 /* Category of message */ 159 160 /* transmit data command block */ 161 #define ARB_XMT_CMDCORR 1 162 #define ARB_XMT_DHBADDR 6 163 164 /* ring status change information block */ 165 #define ARB_RINGSTATUS 6 166 167 /* DLC status change response block */ 168 #define ARB_DLCSTAT_STATUS 6 /* status info field */ 169 #define ARB_DLCSTAT_FRMRDATA 8 /* 5 bytes */ 170 #define ARB_DLCSTAT_ACCPRIO 13 171 #define ARB_DLCSTAT_REMADDR 14 /* remote address */ 172 #define ARB_DLCSTAT_REMSAP 20 /* remote sap */ 173 174 /* 175 * Structure of SRB (System Request Block) 176 */ 177 #define SRB_SIZE 28 /* size of SRB */ 178 #define SRB_CMD 0 179 #define SRB_RETCODE 2 180 181 /* contents of SRB after adapter reset */ 182 #define INIT_COMPL 0x80 /* in SRB_CMD */ 183 #define SRB_INIT_STATUS 1 184 #define RSP_DETECT 0x40 185 #define FAST_PATH_TRANSMIT 0x20 186 #define RING_MEASUREMENT 0x08 187 #define RPL 0x02 188 #define RSP_16 0x01 189 #define SRB_INIT_STATUS2 2 190 #define PNP 0x80 191 #define SET_DEF_RSP 0x40 192 #define AUTO_DEF_RSP_UPDATE 0x20 193 #define SRB_INIT_BUC 6 /* bring up code */ 194 #define SRB_INIT_ENCADDR 8 /* offset of adapter's */ 195 /* permanent encoded address */ 196 #define SRB_INIT_LVLADDR 10 /* offset of adapter's */ 197 /* microcode level */ 198 #define SRB_INIT_ADAPADDR 12 /* offset of adapter addresses */ 199 #define SRB_INIT_PARMSADDR 14 /* offset of adapter parameters */ 200 #define SRB_INIT_MACADDR 16 /* offset of adapter MAC buffer */ 201 #define SRB_INIT_UTILADDR 18 /* offset of ring utilization measurement */ 202 203 /* config fast path ram command block */ 204 #define SRB_CFP_CMDSIZE 12 /* length of command block */ 205 #define SRB_CFP_RAMSIZE 8 206 #define SRB_CFP_BUFSIZE 10 207 208 /* config fast path transmit response block */ 209 #define SRB_CFPRESP_FPXMIT 8 /* offset to transmit control area */ 210 #define SRB_CFPRESP_SRBADDR 10 /* offset for the next SRB address */ 211 212 /* open command block */ 213 #define SRB_OPEN_CMDSIZE 60 214 #define SRB_OPEN_OPTIONS 8 /* open options */ 215 #define SRB_OPEN_NODEADDR 10 /* adapter's ring address */ 216 #define SRB_OPEN_GROUPADDR 16 /* adapter's group address */ 217 #define SRB_OPEN_FUNCTADDR 20 /* adapter's functional address */ 218 #define SRB_OPEN_NUMRCVBUF 24 /* number of receive buffers */ 219 #define SRB_OPEN_RCVBUFLEN 26 /* length of receive buffers */ 220 #define SRB_OPEN_DHBLEN 28 /* length of DHBs */ 221 #define SRB_OPEN_NUMDHB 30 /* number of DHBs */ 222 #define SRB_OPEN_DLCMAXSAP 32 /* max. number of SAPs */ 223 #define SRB_OPEN_DLCMAXSTA 33 /* max. number of link stations */ 224 #define SRB_OPEN_DLCMAXGSAP 34 /* max. number of group SAPs */ 225 #define SRB_OPEN_DLCMAXGMEM 35 /* max. members per group SAP */ 226 #define SRB_OPEN_DLCT1TICK1 36 /* timer T1 intvl. group one */ 227 #define SRB_OPEN_DLCT2TICK1 37 /* timer T7 intvl. group one */ 228 #define SRB_OPEN_DLCTITICK1 38 /* timer Ti intvl. group one */ 229 #define SRB_OPEN_DLCT1TICK2 39 /* timer T1 intvl. group two */ 230 #define SRB_OPEN_DLCT2TICK2 40 /* timer T7 intvl. group two */ 231 #define SRB_OPEN_DLCTITICK2 41 /* timer Ti intvl. group two */ 232 #define SRB_OPEN_PODUCTID 42 /* product id (18 bytes) */ 233 234 /* open command response block */ 235 #define SRB_OPENRESP_ERRCODE 6 236 #define SRB_OPENRESP_ASBADDR 8 /* offset of ASB */ 237 #define SRB_OPENRESP_SRBADDR 10 /* offset of SRB */ 238 #define SRB_OPENRESP_ARBADDR 12 /* offset of ARB */ 239 #define SRB_OPENRESP_SSBADDR 14 /* offset of SSB */ 240 241 /* open sap command and response block */ 242 #define SRB_OPNSAP_STATIONID 4 /* ID of SAP after open */ 243 #define SRB_OPNSAP_TIMERT1 6 /* response timer */ 244 #define SRB_OPNSAP_TIMERT2 7 /* acknowledge timer */ 245 #define SRB_OPNSAP_TIMERTI 8 /* inactivity timer */ 246 #define SRB_OPNSAP_MAXOUT 9 /* max. xmits without ack */ 247 #define SRB_OPNSAP_MAXIN 10 /* max. recvs without ack */ 248 #define SRB_OPNSAP_MAXOUTINCR 11 /* window increment value */ 249 #define SRB_OPNSAP_MAXRETRY 12 /* N2 value */ 250 #define SRB_OPNSAP_GSAPMAXMEMB 13 /* max. SAPs for a group SAP */ 251 #define SRB_OPNSAP_MAXIFIELD 14 /* max recv info field length */ 252 #define SRB_OPNSAP_SAPVALUE 16 /* SAP to be opened */ 253 #define SRB_OPNSAP_SAPOPTIONS 17 /* options to be set */ 254 #define SRB_OPNSAP_STATIONCNT 18 /* num of link stations to reserve */ 255 #define SRB_OPNSAP_SAPGSAPMEMB 19 /* number of GSAP members */ 256 #define SRB_OPNSAP_GSAP1 20 /* first gsap request */ 257 258 /* read log command and response block */ 259 #define SRB_RLOG_LOGDATA 14 /* 14 bytes of log data */ 260 #define SRB_LOG_LINEERRS (SRB_RLOG_LOGDATA+0) /* line errors */ 261 #define SRB_LOG_INTERRS (SRB_RLOG_LOGDATA+1) /* internal errors */ 262 #define SRB_LOG_BRSTERRS (SRB_RLOG_LOGDATA+2) /* burst errors */ 263 #define SRB_LOG_ACERRS (SRB_RLOG_LOGDATA+3) /* AC errors */ 264 #define SRB_LOG_ABRTERRS (SRB_RLOG_LOGDATA+4) /* abort errors */ 265 #define SRB_LOG_LOSTFRMS (SRB_RLOG_LOGDATA+6) /* lost frames */ 266 #define SRB_LOG_RCVCONG (SRB_RLOG_LOGDATA+7) /* receive congestion count */ 267 #define SRB_LOG_FCPYERRS (SRB_RLOG_LOGDATA+8) /* frame copied errors */ 268 #define SRB_LOG_FREQERRS (SRB_RLOG_LOGDATA+9) /* frequency erros */ 269 #define SRB_LOG_TOKENERRS (SRB_RLOG_LOGDATA+10) /* token errors */ 270 271 /* set default ring speed command */ 272 #define SRB_SET_DEFRSP 6 273 274 /* 275 * Structure of ASB (Adapter Status Block) 276 */ 277 #define ASB_SIZE 12 /* size of ASB */ 278 #define RECV_CMD 0 279 #define RECV_RETCODE 2 280 #define RECV_STATIONID 4 281 282 #define RECV_RESP_RECBUFADDR 6 283 284 /* host response to xmit-req-data command */ 285 #define XMIT_CMD 0 286 #define XMIT_CMDCORR 1 /* command correlator */ 287 #define XMIT_RETCODE 2 /* return code */ 288 #define XMIT_STATIONID 4 /* id of sending station */ 289 #define XMIT_FRAMELEN 6 /* length of entire frame */ 290 #define XMIT_HDRLEN 8 /* length of LAN header */ 291 #define XMIT_REMSAP 9 /* remote SAP */ 292 #define XMIT_DATA 10 /* offset of first data byte */ 293 /* fast path specific data */ 294 #define XMIT_LASTBUF 12 295 #define XMIT_FRAMEPTR 14 296 #define XMIT_NEXTBUF 16 297 #define XMIT_STATUS 18 298 #define XMIT_STRIPFS 19 299 #define XMIT_BUFLEN 20 300 #define XMIT_FP_DATA 22 /* offset of first data byte */ 301 302 #if 0 /* XXXchb unused? */ 303 /* 304 * Adapter addresses 305 */ 306 struct adapt_addr { 307 unsigned char node_addr[6]; /* Adapter node address */ 308 unsigned char grp_addr[4]; /* Adapter group address */ 309 unsigned char func_addr[4]; /* Adapter functional address */ 310 }; 311 312 /* 313 * Adapter parameters 314 */ 315 struct param_addr { 316 unsigned char phys_addr[4]; /* Adapter physical address */ 317 unsigned char up_node_addr[6]; /* Next active upstream node 318 * addr */ 319 unsigned char up_phys_addr[4]; /* Next active upstream phys 320 * addr */ 321 unsigned char poll_addr[6]; /* Last poll address */ 322 unsigned char res0[2];/* Reserved */ 323 unsigned char acc_priority[2]; /* Transmit access priority */ 324 unsigned char src_class[2]; /* Source class authorization */ 325 unsigned char att_code[2]; /* Last attention code */ 326 unsigned char src_addr[6]; /* Last source address */ 327 unsigned char bcon_type[2]; /* Last beacon type */ 328 unsigned char major_vector[2]; /* Last major vector */ 329 unsigned char ring_stat[2]; /* ring status */ 330 unsigned char soft_error[2]; /* soft error timer value */ 331 unsigned char fe_error[2]; /* front end error counter */ 332 unsigned char next_state[2]; /* next state indicator */ 333 unsigned char mon_error[2]; /* Monitor error code */ 334 unsigned char bcon_xmit[2]; /* Beacon transmit type */ 335 unsigned char bcon_receive[2]; /* Beacon receive type */ 336 unsigned char frame_correl[2]; /* Frame correlator save */ 337 unsigned char bcon_naun[6]; /* beacon station NAUN */ 338 unsigned char res1[4];/* Reserved */ 339 unsigned char bcon_phys[4]; /* Beacon station physical addr */ 340 }; 341 #endif 342 343 #define TXCA_BUFFER_COUNT 0 344 #define TXCA_FREE_QUEUE_HEAD 2 345 #define TXCA_FREE_QUEUE_TAIL 4 346 #define TXCA_ADAPTER_QUEUE_HEAD 6 347 #define TXCA_BUFFER_SIZE 8 348 #define TXCA_COMPLETION_QUEUE_TAIL 10 349 350 /* Adapter receive buffer structure */ 351 #define RB_NEXTBUF 2 /* offset of next buf plus 2 in sram */ 352 #define RB_FS 5 /* FS/addr match (last buf only) */ 353 #define RB_BUFLEN 6 /* length of data in this buffer */ 354 #define RB_DATA 8 /* RCV_BUF_DLEN bytes frame data */ 355 356 /* Misc. structure sizes. */ 357 #define SAPCB_SIZE 64 /* size of SAP control block */ 358 #define LSCB_SIZE 144 /* size of DLC link station control block */ 359 360 /* memory in shared ram area that is reserved by the adapter */ 361 #define PRIVRAM_SIZE 1416 /* adapter private ram area */ 362 #define RESVDMEM_SIZE (PRIVRAM_SIZE+ARB_SIZE+SSB_SIZE+SRB_SIZE+ASB_SIZE) 363 364 /* Memory offsets of adapter control areas */ 365 366 #define TR_SRAM_DEFAULT 0xd8000 367 368 /* Offset of MMIO region */ 369 #define TR_MMIO_OFFSET 0x80000 370 #define TR_MMIO_MINADDR 0xc0000 371 #define TR_MMIO_MAXADDR 0xde000 372 #define TR_MMIO_SIZE 8192 373 374 #define TR_ACA_OFFSET 0x1e00 /* Offset of ACA in MMIO region */ 375 /* 376 * XXX Create AIP structure 377 */ 378 #define TR_MAC_OFFSET 0x1f00 /* Offset of MAC address in MMIO region */ 379 #define TR_ID_OFFSET 0x1f30 /* Offset of ID in MMIO region */ 380 #define TR_TYP_OFFSET 0x1fa0 /* Offset of TYP in MMIO region */ 381 #define TR_RATES_OFFSET 0x1fa2 /* Offset of supported speeds in MMIO region */ 382 #define TR_RAM_OFFSET 0x1fa6 /* Offset of available shared RAM */ 383 #define TR_PAGE_OFFSET 0x1fa8 /* Offset of shared-RAM paging support */ 384 #define TR_DHB4_OFFSET 0x1faa /* Offset of available DHB size at 4Mbit */ 385 #define TR_DHB16_OFFSET 0x1fac /* Offset of available DHB size at 16Mbit */ 386 #define TR_MEDIAS_OFFSET 0x1fb6 /* Offset of supported media types in MMIO */ 387 #define TR_MEDIA_OFFSET 0x1fb8 /* Offset of selected media type in MMIO */ 388 #define TR_IRQ_OFFSET 0x1fba /* Offset of IRQs supported in MMIO region */ 389 390 /* Bring-Up Test results */ 391 392 #define BUT_OK 0x0000 /* Initialization completed OK */ 393 #define BUT_PROCESSOR_FAIL 0x0020 /* Failed processor initialization */ 394 #define BUT_ROM_FAIL 0x0022 /* Failed ROM test diagnostic */ 395 #define BUT_RAM_FAIL 0x0024 /* Failed RAM test diagnostic */ 396 #define BUT_INST_FAIL 0x0026 /* Failed instruction test diag. */ 397 #define BUT_INTER_FAIL 0x0028 /* Failed interrupt test diagnostic */ 398 #define BUT_MEM_FAIL 0x002a /* Failed memory interface diag. */ 399 #define BUT_PROTOCOL_FAIL 0x002c /* Failed protocol handler diag. */ 400 401 402 /* Direct PC-to-adapter commands */ 403 404 #define DIR_INTERRUPT 0x00 /* Cause adapter to interrupt the PC */ 405 #define DIR_MOD_OPEN_PARAMS 0x01 /* Modify open options */ 406 #define DIR_RESTORE_OPEN_PARMS 0x02 /* Restore open options */ 407 #define DIR_OPEN_ADAPTER 0x03 /* Open the adapter card */ 408 #define DIR_CLOSE 0x04 /* Close adapter card */ 409 #define DIR_SET_GRP_ADDR 0x06 /* Set adapter group address */ 410 #define DIR_SET_FUNC_ADDR 0x07 /* Set adapter functional addr */ 411 #define DIR_READ_LOG 0x08 /* Read and reset error counters */ 412 #define DIR_SET_BRIDGE_PARMS 0x09 413 #define DIR_CONFIG_BRIDGE_RAM 0x0c 414 #define DIR_CONFIG_FAST_PATH_RAM 0x12 415 #define DIR_SINGLE_ROUTE_BROADCAST 0x1f 416 #define DIR_SET_DEFAULT_RING_SPEED 0x21 417 418 #define XMIT_DIR_FRAME 0x0a /* Direct station transmit */ 419 #define XMIT_I_FRAME 0x0b 420 #define XMIT_UI_FRM 0x0d /* transmit unnumbered info frame */ 421 #define XMIT_XID_CMD 0x0e /* transmit XID command */ 422 #define XMIT_XID_RESP_FINAL 0x0f 423 #define XMIT_XID_RESP_NOT_FINAL 0x10 424 #define XMIT_TEST_CMD 0x11 /* transmit TEST command */ 425 426 427 /* Adapter-Card-to-PC commands */ 428 429 #define REC_DATA 0x81 /* Data received from ring station */ 430 #define XMIT_DATA_REQ 0x82 /* Adapter needs data to xmit */ 431 #define DLC_STATUS 0x83 /* DLC status has changed */ 432 #define RING_STAT_CHANGE 0x84 /* Adapter has new ring-status info */ 433 #define REC_BRIDGE_DATA 0x85 434 #define REXMIT_DATA_REQ 0x86 435 436 /* Open options */ 437 438 #define OPEN_WRAP 0x8000 /* Wrap xmit data to receive data */ 439 #define OPEN_NO_HARD_ERR 0x4000 /* Ring hard error and xmit beacon */ 440 /* conditions do not cause interrupt */ 441 #define OPEN_NO_SOFT_ERR 0x2000 /* Ring soft errors do not cause */ 442 /* interrupt */ 443 #define OPEN_PASS_MAC 0x1000 /* Pass all adapter-class MAC frames */ 444 /* received but not supported by the */ 445 /* adapter */ 446 #define OPEN_PASS_ATTN_MAC 0x0800 /* Pass all attention-class MAC */ 447 /* frames != the previously received */ 448 /* attention MAC frame */ 449 #define OPEN_PASS_BCON_MAC 0x0100 /* Pass the first beacon MAC frame */ 450 /* and all subsequent beacon MAC */ 451 /* frames that have a change in */ 452 /* source address or beacon type */ 453 #define OPEN_CONT 0x0080 /* Adapter will participate in */ 454 /* monitor contention */ 455 456 #define NUM_RCV_BUF 4 /* Number of receive buffers in */ 457 /* shared RAM needed for adapter to */ 458 /* open */ 459 #define RCV_BUF_LEN 520 /* Length of each receive buffer */ 460 #define RCV_BUF_DLEN RCV_BUF_LEN - 8 /* Length of data in rec buf */ 461 462 #define DHB_LENGTH 512 /* Length of each transmit buffer */ 463 #define FP_BUF_LEN 536 /* length of each FP transmit buffer */ 464 465 /* 466 * Integrity cannot be guaranteed if number of dhbs > 2 467 */ 468 #define NUM_DHB 1 /* Number of transmit buffers */ 469 470 #define DLC_MAX_SAP 0 /* MAX number of SAPs */ 471 #define DLC_MAX_STA 0 /* MAX number of link stations */ 472 #define DLC_MAX_GSAP 0 /* MAX number of group SAPs */ 473 #define DLC_MAX_GMEM 0 /* MAX number of SAPs that can be */ 474 /* assigned to any given group */ 475 #define DLC_TICK 0 /* Zero selects default of 40ms */ 476 477 478 /* Open return codes */ 479 480 #define OPEN_OK 0x00 /* Open completed successfully */ 481 #define OPEN_BAD_COMMAND 0x01 /* Invalid command code */ 482 #define OPEN_ALREADY 0x03 /* Adapter is ALREADY open */ 483 #define OPEN_MISSING_PARAMS 0x05 /* Required parameters missing */ 484 #define OPEN_UNRECOV_FAIL 0x07 /* Unrecoverable failure occurred */ 485 #define OPEN_INAD_REC_BUFS 0x30 /* Inadequate receive buffers */ 486 #define OPEN_BAD_NODE_ADDR 0x32 /* Invalid NODE address */ 487 #define OPEN_BAD_REC_BUF_LEN 0x33 /* Invalid receive buffer length */ 488 #define OPEN_BAD_XMIT_BUF_LEN 0x43 /* Invalid transmit buffer length */ 489 490 /* Bit definitions of ISRA High Byte, (Adapter Status) */ 491 #define PARITY_ERROR 0x80 /* Parity error on the adapter's internal bus */ 492 #define TIMER_STAT 0x40 /* A Timer Control Reg. has an interrupt */ 493 #define ACCESS_STAT 0x20 /* Shared RAM or MMIO access violation */ 494 #define DEADMAN_TIMER 0x10 /* The deadman timer has expired */ 495 #define PROCESSOR_CK 0x08 /* Adapter Processor Check */ 496 #define H_INT_MASK 0x02 /* When on, no adapter hardware interrupts */ 497 #define S_INT_MASK 0x01 /* When on, no adapter software interrupts */ 498 499 /* Bit definitions of ISRA Low Byte, (Used by PC to interrupt adapter) */ 500 #define XMIT_REQ 0x40 /* Transmit frame in fast path transmit buf */ 501 #define CMD_IN_SRB 0x20 /* Inform adapter of command in SRB */ 502 #define RESP_IN_ASB 0x10 /* Inform adapter of response in ASB */ 503 #define SRB_FREE 0x08 /* Inform PC when SRB is FREE */ 504 #define ASB_FREE 0x04 /* Inform PC when ASB is FREE */ 505 #define ARB_FREE 0x02 /* Inform adapter ARB is FREE */ 506 #define SSB_FREE 0x01 /* Inform adapter SSB is FREE */ 507 508 /* Bit definitions of ISRP High Byte, (PC interrupts and interrupt control) */ 509 #define NMI_INT_CTL 0x80 /* 1 = all interrupts to PC interrupt level */ 510 /* 0 = error and timer interrupts to PC NMI */ 511 #define INT_ENABLE 0x40 /* Allow adapter to interrupt the PC */ 512 #define TCR_INT 0x10 /* Timer Control Reg. has interrupt for PC */ 513 #define ERR_INT 0x08 /* Adap machine check, deadman timer, overrun */ 514 #define ACCESS_INT 0x04 /* Shared RAM or MMIO access violation */ 515 #define SHARED_INT_BLK 0x02 /* Shared interrupt blocked */ 516 #define PRIM_ALT_ADDR 0x01 /* 0 = primary adapter address */ 517 /* 1 = alternate adapter address */ 518 519 /* Bit definitions of ISRP Low Byte, (PC interrupts) */ 520 #define ADAP_CHK_INT 0x40 /* The adapter has an unrecoverable error */ 521 #define SRB_RESP_INT 0x20 /* Adapter has placed a response in the SRB */ 522 #define ASB_FREE_INT 0x10 /* Adapter has read response in ARB */ 523 #define ARB_CMD_INT 0x08 /* ARB has command for PC to act on */ 524 #define SSB_RESP_INT 0x04 /* SSB has response to previous SRB command */ 525 #define XMIT_COMPLETE 0x02 /* Fast path transmit frame complete */ 526 527 528 /* Constants for Token-Ring physical header */ 529 #define DLC_HDR_LEN 0x3 /* Length of DLC header */ 530 #define SNAP_LENGTH 0x05 /* SNAP field length */ 531 /* protocol id = 3 bytes */ 532 /* ethertype = 2 bytes */ 533 #define HDR_LNGTH_NOROUTE 14 /* length of header with no route info */ 534 #define SKIP_DSAP_SSAP 0x02 /* length of dsap and ssap in llc frame */ 535 #define TR_MAX_LINK_HDR 46 /* max length of link header with route info */ 536 537 /* SAP DLC SRB commands (page 6-50 Token Ring Tech. Ref.) */ 538 #define DLC_RESET 0x14 539 #define DLC_OPEN_SAP 0x15 /* activate service access point */ 540 #define DLC_CLOSE_SAP 0x16 /* de-activate SAP */ 541 #define DLC_REALLOCATE 0x17 542 #define DLC_OPEN_STATION 0x19 543 #define DLC_CLOSE_STATION 0x1a 544 #define DLC_CONNECT_STATION 0x1b 545 #define DLC_MODIFY 0x1c 546 #define DLC_FLOW_CONTROL 0x1d 547 #define DLC_STATISTICS 0x1e 548 549 550 /* ARB RING STATUS CHANGE */ 551 #define SIGNAL_LOSS 0x8000 /* signal loss */ 552 #define HARD_ERR 0x4000 /* beacon frames sent */ 553 #define SOFT_ERR 0x2000 /* soft error */ 554 #define LOBE_FAULT 0x0800 /* lobe wire fault */ 555 #define LOG_OFLOW 0x0080 /* adapter error log counter overflow */ 556 #define SINGLE_STATION 0x0040 /* single station on ring */ 557