1 /*- 2 * Copyright (c) 2005, Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* Machine dependent interfaces */ 30 31 #ifndef _DEV_HWPMC_AMD_H_ 32 #define _DEV_HWPMC_AMD_H_ 1 33 34 /* AMD K7 and K8 PMCs */ 35 36 #define AMD_PMC_EVSEL_0 0xC0010000 37 #define AMD_PMC_EVSEL_1 0xC0010001 38 #define AMD_PMC_EVSEL_2 0xC0010002 39 #define AMD_PMC_EVSEL_3 0xC0010003 40 #define AMD_PMC_EVSEL_4 0xC0010208 41 #define AMD_PMC_EVSEL_5 0xC001020A 42 43 #define AMD_PMC_PERFCTR_0 0xC0010004 44 #define AMD_PMC_PERFCTR_1 0xC0010005 45 #define AMD_PMC_PERFCTR_2 0xC0010006 46 #define AMD_PMC_PERFCTR_3 0xC0010007 47 #define AMD_PMC_PERFCTR_4 0xC0010209 48 #define AMD_PMC_PERFCTR_5 0xC001020B 49 50 #define AMD_NPMCS 6 51 52 #define AMD_PMC_COUNTERMASK 0xFF000000 53 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 54 #define AMD_PMC_INVERT (1 << 23) 55 #define AMD_PMC_ENABLE (1 << 22) 56 #define AMD_PMC_INT (1 << 20) 57 #define AMD_PMC_PC (1 << 19) 58 #define AMD_PMC_EDGE (1 << 18) 59 #define AMD_PMC_OS (1 << 17) 60 #define AMD_PMC_USR (1 << 16) 61 62 #define AMD_PMC_UNITMASK_M 0x10 63 #define AMD_PMC_UNITMASK_O 0x08 64 #define AMD_PMC_UNITMASK_E 0x04 65 #define AMD_PMC_UNITMASK_S 0x02 66 #define AMD_PMC_UNITMASK_I 0x01 67 #define AMD_PMC_UNITMASK_MOESI 0x1F 68 #define AMD_PMC_UNITMASK 0xFF00 69 #if defined(__i386__) 70 #define AMD_PMC_EVENTMASK 0x00FF 71 #define AMD_PMC_TO_EVENTMASK(x) ((x) & 0xFF) 72 #elif defined(__amd64__) 73 #define AMD_PMC_EVENTMASK 0xF000000FF 74 #define AMD_PMC_TO_EVENTMASK(x) ((x) & 0x0FFF) 75 #define AMD_PMC_EXTENDEDEVBIT 24 76 #define AMD_PMC_EVENTMASK_EXT 0x0FF 77 #define AMD_PMC_EXTENDEDEVMASK 0xF00 78 #endif 79 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 80 81 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 82 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 83 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 84 85 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 86 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 87 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 88 89 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 90 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 91 92 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 93 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 94 #define AMD_LEGACY_COUNTERS 4 95 #define AMD_FAM17H_COUNTERS 6 96 struct pmc_md_amd_op_pmcallocate { 97 #if defined(__i386__) 98 uint32_t pm_amd_config; 99 #elif defined(__amd64__) 100 uint64_t pm_amd_config; 101 #endif 102 }; 103 104 #ifdef _KERNEL 105 106 /* MD extension for 'struct pmc' */ 107 struct pmc_md_amd_pmc { 108 #if defined(__i386__) 109 uint32_t pm_amd_evsel; 110 #elif defined(__amd64__) 111 uint64_t pm_amd_evsel; 112 #endif 113 }; 114 115 #endif /* _KERNEL */ 116 #endif /* _DEV_HWPMC_AMD_H_ */ 117