1 /* $OpenBSD: ahareg.h,v 1.4 2002/06/07 20:41:06 niklas Exp $ */ 2 typedef u_int8_t physaddr[3]; 3 typedef u_int8_t physlen[3]; 4 #define ltophys _lto3b 5 #define phystol _3btol 6 7 /* 8 * I/O port offsets 9 */ 10 #define AHA_CTRL_PORT 0 /* control (wo) */ 11 #define AHA_STAT_PORT 0 /* status (ro) */ 12 #define AHA_CMD_PORT 1 /* command (wo) */ 13 #define AHA_DATA_PORT 1 /* data (ro) */ 14 #define AHA_INTR_PORT 2 /* interrupt status (ro) */ 15 16 /* 17 * AHA_CTRL bits 18 */ 19 #define AHA_CTRL_HRST 0x80 /* Hardware reset */ 20 #define AHA_CTRL_SRST 0x40 /* Software reset */ 21 #define AHA_CTRL_IRST 0x20 /* Interrupt reset */ 22 #define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */ 23 24 /* 25 * AHA_STAT bits 26 */ 27 #define AHA_STAT_STST 0x80 /* Self test in Progress */ 28 #define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */ 29 #define AHA_STAT_INIT 0x20 /* Mbx Init required */ 30 #define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */ 31 #define AHA_STAT_CDF 0x08 /* cmd/data out port full */ 32 #define AHA_STAT_DF 0x04 /* Data in port full */ 33 #define AHA_STAT_INVDCMD 0x01 /* Invalid command */ 34 35 /* 36 * AHA_CMD opcodes 37 */ 38 #define AHA_NOP 0x00 /* No operation */ 39 #define AHA_MBX_INIT 0x01 /* Mbx initialization */ 40 #define AHA_START_SCSI 0x02 /* start scsi command */ 41 #define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */ 42 #define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */ 43 #if 0 44 #define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */ 45 #define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */ 46 #define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */ 47 #define AHA_SPEED_SET 0x09 /* set transfer speed */ 48 #endif 49 #define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */ 50 #define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */ 51 #define AHA_TARGET_EN 0x0c /* enable target mode */ 52 #define AHA_INQUIRE_SETUP 0x0d /* return setup data */ 53 #define AHA_ECHO 0x1e /* Echo command data */ 54 #define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */ 55 #define AHA_EXT_BIOS 0x28 /* return extended bios info */ 56 #define AHA_MBX_ENABLE 0x29 /* enable mail box interface */ 57 58 /* 59 * AHA_INTR bits 60 */ 61 #define AHA_INTR_ANYINTR 0x80 /* Any interrupt */ 62 #define AHA_INTR_SCRD 0x08 /* SCSI reset detected */ 63 #define AHA_INTR_HACC 0x04 /* Command complete */ 64 #define AHA_INTR_MBOA 0x02 /* MBX out empty */ 65 #define AHA_INTR_MBIF 0x01 /* MBX in full */ 66 67 struct aha_mbx_out { 68 u_char cmd; 69 physaddr ccb_addr; 70 }; 71 72 struct aha_mbx_in { 73 u_char stat; 74 physaddr ccb_addr; 75 }; 76 77 /* 78 * mbo.cmd values 79 */ 80 #define AHA_MBO_FREE 0x0 /* MBO entry is free */ 81 #define AHA_MBO_START 0x1 /* MBO activate entry */ 82 #define AHA_MBO_ABORT 0x2 /* MBO abort entry */ 83 84 /* 85 * mbi.stat values 86 */ 87 #define AHA_MBI_FREE 0x0 /* MBI entry is free */ 88 #define AHA_MBI_OK 0x1 /* completed without error */ 89 #define AHA_MBI_ABORT 0x2 /* aborted ccb */ 90 #define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */ 91 #define AHA_MBI_ERROR 0x4 /* Completed with error */ 92 93 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */ 94 #define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */ 95 /* allow 64 K i/o (min) */ 96 97 struct aha_scat_gath { 98 physlen seg_len; 99 physaddr seg_addr; 100 }; 101 102 struct aha_ccb { 103 u_char opcode; 104 u_char lun:3; 105 u_char data_in:1; /* must be 0 */ 106 u_char data_out:1; /* must be 0 */ 107 u_char target:3; 108 u_char scsi_cmd_length; 109 u_char req_sense_length; 110 physlen data_length; 111 physaddr data_addr; 112 physaddr link_addr; 113 u_char link_id; 114 u_char host_stat; 115 u_char target_stat; 116 u_char reserved[2]; 117 struct scsi_generic scsi_cmd; 118 struct scsi_sense_data scsi_sense; 119 struct aha_scat_gath scat_gath[AHA_NSEG]; 120 /*----------------------------------------------------------------*/ 121 #define CCB_PHYS_SIZE ((int)&((struct aha_ccb *)0)->chain) 122 TAILQ_ENTRY(aha_ccb) chain; 123 struct aha_ccb *nexthash; 124 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 125 int flags; 126 #define CCB_ALLOC 0x01 127 #define CCB_ABORT 0x02 128 #ifdef AHADIAG 129 #define CCB_SENDING 0x04 130 #endif 131 int timeout; 132 bus_dmamap_t dmam; 133 bus_dmamap_t ccb_dmam; 134 }; 135 136 /* 137 * opcode fields 138 */ 139 #define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */ 140 #define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */ 141 #define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */ 142 #define AHA_RESET_CCB 0x81 /* SCSI Bus reset */ 143 144 /* 145 * aha_ccb.host_stat values 146 */ 147 #define AHA_OK 0x00 /* cmd ok */ 148 #define AHA_LINK_OK 0x0a /* Link cmd ok */ 149 #define AHA_LINK_IT 0x0b /* Link cmd ok + int */ 150 #define AHA_SEL_TIMEOUT 0x11 /* Selection time out */ 151 #define AHA_OVER_UNDER 0x12 /* Data over/under run */ 152 #define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */ 153 #define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */ 154 #define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */ 155 #define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */ 156 #define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */ 157 #define AHA_INV_TARGET 0x18 /* Invalid target direction */ 158 #define AHA_CCB_DUP 0x19 /* Duplicate CCB received */ 159 #define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */ 160 161 struct aha_revision { 162 struct { 163 u_char opcode; 164 } cmd; 165 struct { 166 u_char boardid; /* type of board */ 167 /* 0x31 = AHA-1540 */ 168 /* 0x41 = AHA-1540A/1542A/1542B */ 169 /* 0x42 = AHA-1640 */ 170 /* 0x43 = AHA-1542C */ 171 /* 0x44 = AHA-1542CF */ 172 /* 0x45 = AHA-1542CF, BIOS v2.01 */ 173 /* 0x46 = AHA-1542CP */ 174 u_char spec_opts; /* special options ID */ 175 /* 0x41 = Board is standard model */ 176 u_char revision_1; /* firmware revision [0-9A-Z] */ 177 u_char revision_2; /* firmware revision [0-9A-Z] */ 178 } reply; 179 }; 180 181 struct aha_extbios { 182 struct { 183 u_char opcode; 184 } cmd; 185 struct { 186 u_char flags; /* Bit 3 == 1 extended bios enabled */ 187 u_char mailboxlock; /* mail box lock code to unlock it */ 188 } reply; 189 }; 190 191 struct aha_toggle { 192 struct { 193 u_char opcode; 194 u_char enable; 195 } cmd; 196 }; 197 198 struct aha_config { 199 struct { 200 u_char opcode; 201 } cmd; 202 struct { 203 u_char chan; 204 u_char intr; 205 u_char scsi_dev:3; 206 u_char :5; 207 } reply; 208 }; 209 210 struct aha_mailbox { 211 struct { 212 u_char opcode; 213 u_char nmbx; 214 physaddr addr; 215 } cmd; 216 }; 217 218 struct aha_unlock { 219 struct { 220 u_char opcode; 221 u_char junk; 222 u_char magic; 223 } cmd; 224 }; 225 226 struct aha_devices { 227 struct { 228 u_char opcode; 229 } cmd; 230 struct { 231 u_char junk[8]; 232 } reply; 233 }; 234 235 struct aha_setup { 236 struct { 237 u_char opcode; 238 u_char len; 239 } cmd; 240 struct { 241 u_char sync_neg:1; 242 u_char parity:1; 243 u_char :6; 244 u_char speed; 245 u_char bus_on; 246 u_char bus_off; 247 u_char num_mbx; 248 u_char mbx[3]; 249 struct { 250 u_char offset:4; 251 u_char period:3; 252 u_char valid:1; 253 } sync[8]; 254 u_char disc_sts; 255 } reply; 256 }; 257 258 #define INT9 0x01 259 #define INT10 0x02 260 #define INT11 0x04 261 #define INT12 0x08 262 #define INT14 0x20 263 #define INT15 0x40 264 265 #define EISADMA 0x00 266 #define CHAN0 0x01 267 #define CHAN5 0x20 268 #define CHAN6 0x40 269 #define CHAN7 0x80 270