| /openbsd/src/sys/dev/pci/drm/i915/display/ |
| D | intel_color_regs.h | 33 #define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ argument
42 #define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ argument
48 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) argument
65 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) argument
69 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1… argument
73 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) argument
120 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_G… argument
121 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) argument
122 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_G… argument
123 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) argument
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| D | intel_pipe_crc_regs.h | 12 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) argument
63 #define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) argument
67 #define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) argument
71 #define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I9… argument
75 #define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) argument
79 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) argument
82 #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) argument
85 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) argument
88 #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_… argument
91 #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A… argument
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| D | intel_dsb_regs.h | 13 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ argument
15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) argument
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) argument
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) argument
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) argument
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) argument
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) argument
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) argument
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) argument
53 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) argument
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| D | intel_display_irq.c | 28 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank()
110 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq()
135 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq()
141 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq()
183 enum pipe pipe) in i915_pipestat_enable_mask()
227 enum pipe pipe, u32 status_mask) in i915_enable_pipestat()
250 enum pipe pipe, u32 status_mask) in i915_disable_pipestat()
303 enum pipe pipe, in display_pipe_crc_irq_handler()
338 enum pipe pipe, in display_pipe_crc_irq_handler()
345 enum pipe pipe) in flip_done_handler()
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| D | intel_sprite_regs.h | 12 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) argument
37 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) argument
41 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) argument
45 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) argument
53 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) argument
61 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) argument
65 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) argument
69 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) argument
74 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) argument
78 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) argument
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| D | intel_vdsc_regs.h | 31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
60 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
63 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
66 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ argument
69 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ argument
72 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) argument
73 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) argument
202 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
205 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
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| D | intel_cursor_regs.h | 12 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) argument
28 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) argument
44 #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) argument
47 #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) argument
56 #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) argument
59 #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) argument
66 #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) argument
72 #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) argument
75 #define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) argument
80 #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) argument
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| D | skl_universal_plane_regs.h | 11 #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
13 #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
15 #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
17 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
20 #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_… argument
26 #define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a,… argument
35 #define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ argument
106 #define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ argument
116 #define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ argument
128 #define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ argument
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| D | intel_fdi.c | 27 enum pipe pipe, bool state) in assert_fdi_tx()
49 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_enabled()
54 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_disabled()
60 enum pipe pipe, bool state) in assert_fdi_rx()
70 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_enabled()
75 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_disabled()
81 enum pipe pipe) in assert_fdi_tx_pll_enabled()
99 enum pipe pipe, bool state) in assert_fdi_rx_pll()
109 void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_pll_enabled()
114 void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_pll_disabled()
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| D | intel_audio_regs.h | 20 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ argument
24 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ argument
35 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) argument
38 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) argument
43 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) argument
46 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) argument
51 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) argument
54 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) argument
57 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) argument
137 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) argument
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| D | intel_pch_display.c | 39 enum pipe pipe, enum port port, in assert_pch_dp_disabled()
58 enum pipe pipe, enum port port, in assert_pch_hdmi_disabled()
77 enum pipe pipe) in assert_pch_ports_disabled()
102 enum pipe pipe) in assert_pch_transcoder_disabled()
179 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_set_m1_n1() local
190 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_set_m2_n2() local
201 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m1_n1() local
212 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m2_n2() local
247 enum pipe pipe = crtc->pipe; in ilk_enable_pch_transcoder() local
313 enum pipe pipe = crtc->pipe; in ilk_disable_pch_transcoder() local
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| D | intel_fifo_underrun.c | 62 enum pipe pipe; in ivb_can_enable_err_int() local
79 enum pipe pipe; in cpt_can_enable_serr_int() local
114 enum pipe pipe, in i9xx_set_fifo_underrun_reporting()
136 enum pipe pipe, bool enable) in ilk_set_fifo_underrun_reporting()
151 enum pipe pipe = crtc->pipe; in ivb_check_fifo_underruns() local
167 enum pipe pipe, bool enable, in ivb_set_fifo_underrun_reporting()
205 enum pipe pipe, bool enable) in bdw_set_fifo_underrun_reporting()
283 enum pipe pipe, bool enable) in __intel_set_cpu_fifo_underrun_reporting()
323 enum pipe pipe, bool enable) in intel_set_cpu_fifo_underrun_reporting()
396 enum pipe pipe) in intel_cpu_fifo_underrun_irq_handler()
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| D | intel_pipe_crc.c | 77 enum pipe pipe, in i9xx_pipe_crc_auto_source()
127 enum pipe pipe, in vlv_pipe_crc_ctl_reg()
194 enum pipe pipe, in i9xx_pipe_crc_ctl_reg()
231 enum pipe pipe) in vlv_undo_pipe_scramble_reset()
332 enum pipe pipe, in ivb_pipe_crc_ctl_reg()
360 enum pipe pipe, in skl_pipe_crc_ctl_reg()
403 enum pipe pipe, in get_new_crc_ctl_reg()
584 enum pipe pipe = crtc->pipe; in intel_crtc_set_crc_source() local
635 enum pipe pipe = crtc->pipe; in intel_crtc_enable_pipe_crc() local
655 enum pipe pipe = crtc->pipe; in intel_crtc_disable_pipe_crc() local
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| D | intel_display_reg_defs.h | 18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
32 #define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c… argument
33 #define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c… argument
39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \ argument
45 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \ argument
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| D | skl_universal_plane.c | 601 enum pipe pipe = plane->pipe; in icl_program_input_csc() local
727 enum pipe pipe = plane->pipe; in skl_write_plane_wm() local
765 enum pipe pipe = plane->pipe; in skl_plane_disable_arm() local
777 enum pipe pipe = plane->pipe; in icl_plane_disable_sel_fetch_arm() local
791 enum pipe pipe = plane->pipe; in icl_plane_disable_arm() local
805 enum pipe *pipe) in skl_plane_get_hw_state()
1241 enum pipe pipe = plane->pipe; in icl_plane_csc_load_black() local
1277 enum pipe pipe = plane->pipe; in skl_plane_update_noarm() local
1307 enum pipe pipe = plane->pipe; in skl_plane_update_arm() local
1367 enum pipe pipe = plane->pipe; in icl_plane_update_sel_fetch_noarm() local
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| D | intel_sprite.c | 51 static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) in sprite_name()
144 enum pipe pipe = plane->pipe; in vlv_sprite_update_clrc() local
362 enum pipe pipe = plane->pipe; in vlv_sprite_update_gamma() local
386 enum pipe pipe = plane->pipe; in vlv_sprite_update_noarm() local
408 enum pipe pipe = plane->pipe; in vlv_sprite_update_arm() local
456 enum pipe pipe = plane->pipe; in vlv_sprite_disable_arm() local
465 enum pipe *pipe) in vlv_sprite_get_hw_state()
772 enum pipe pipe = plane->pipe; in ivb_sprite_update_gamma() local
804 enum pipe pipe = plane->pipe; in ivb_sprite_update_noarm() local
835 enum pipe pipe = plane->pipe; in ivb_sprite_update_arm() local
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| D | intel_fdi_regs.h | 28 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) argument
33 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) argument
83 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) argument
119 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) argument
125 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) argument
126 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) argument
145 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) argument
146 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) argument
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| D | intel_color.c | 212 enum pipe pipe = crtc->pipe; in ilk_update_pipe_csc() local
245 enum pipe pipe = crtc->pipe; in ilk_read_pipe_csc() local
311 enum pipe pipe = crtc->pipe; in icl_update_output_csc() local
341 enum pipe pipe = crtc->pipe; in icl_read_output_csc() local
618 enum pipe pipe = crtc->pipe; in vlv_load_wgc_csc() local
640 enum pipe pipe = crtc->pipe; in vlv_read_wgc_csc() local
720 enum pipe pipe = crtc->pipe; in chv_load_cgm_csc() local
738 enum pipe pipe = crtc->pipe; in chv_read_cgm_csc() local
1083 enum pipe pipe = crtc->pipe; in skl_color_commit_arm() local
1111 enum pipe pipe = crtc->pipe; in icl_color_commit_arm() local
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| /openbsd/src/sys/sys/ |
| D | pipe.h | 80 struct pipe { struct
81 struct rwlock *pipe_lock; argument
82 struct pipebuf pipe_buffer; /* [p] data storage */ argument
83 struct klist pipe_klist; /* [p] list of knotes */ argument
84 struct timespec pipe_atime; /* [p] time of last access */ argument
85 struct timespec pipe_mtime; /* [p] time of last modify */ argument
86 struct timespec pipe_ctime; /* [I] time of status change */ argument
87 struct sigio_ref pipe_sigio; /* [S] async I/O registration */ argument
88 struct pipe *pipe_peer; /* [p] link with other direction */ argument
89 struct pipe_pair *pipe_pair; /* [I] pipe storage */ argument
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| /openbsd/src/sys/dev/pci/drm/ |
| D | drm_vblank.c | 170 drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) in drm_vblank_crtc()
182 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank()
198 static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_max_vblank_count()
209 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter()
215 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter()
239 static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe) in drm_reset_vblank_timestamp()
286 static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, in drm_update_vblank_count()
378 u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_vblank_count()
414 unsigned int pipe = drm_crtc_index(crtc); in drm_crtc_accurate_vblank_count() local
433 static void __disable_vblank(struct drm_device *dev, unsigned int pipe) in __disable_vblank()
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| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | mes_v12_0.c | 145 int pipe, void *pkt, int size, in mes_v12_0_submit_pkt_and_poll_completion()
357 int pipe; in mes_v12_0_reset_hw_queue() local
383 int pipe; in mes_v12_0_map_legacy_queue() local
414 int pipe; in mes_v12_0_unmap_legacy_queue() local
461 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) in mes_v12_0_query_sched_status()
480 int pipe; in mes_v12_0_misc_op() local
544 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe) in mes_v12_0_set_hw_resources_1()
560 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) in mes_v12_0_set_hw_resources()
711 int pipe; in mes_v12_0_reset_legacy_queue() local
758 enum admgpu_mes_pipe pipe) in mes_v12_0_allocate_ucode_buffer()
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| D | mes_v11_0.c | 771 enum admgpu_mes_pipe pipe) in mes_v11_0_allocate_ucode_buffer()
806 enum admgpu_mes_pipe pipe) in mes_v11_0_allocate_ucode_data_buffer()
847 enum admgpu_mes_pipe pipe) in mes_v11_0_free_ucode_buffers()
860 int pipe; in mes_v11_0_get_fw_version() local
883 uint32_t pipe, data = 0; in mes_v11_0_enable() local
935 enum admgpu_mes_pipe pipe, bool prime_icache) in mes_v11_0_load_microcode()
1007 enum admgpu_mes_pipe pipe) in mes_v11_0_allocate_eop_buf()
1218 enum admgpu_mes_pipe pipe) in mes_v11_0_queue_init()
1301 enum admgpu_mes_pipe pipe) in mes_v11_0_mqd_sw_init()
1342 int pipe, r; in mes_v11_0_sw_init() local
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| /openbsd/src/sys/dev/pci/drm/i915/ |
| D | vlv_sideband_reg.h | 49 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
50 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
51 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
52 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) argument
53 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) argument
54 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) argument
55 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) argument
56 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) argument
57 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) argument
58 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) argument
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| /openbsd/src/sys/dev/usb/ |
| D | usbdi.c | 148 usbd_dump_queue(struct usbd_pipe *pipe) in usbd_dump_queue()
159 usbd_dump_pipe(struct usbd_pipe *pipe) in usbd_dump_pipe()
176 struct usbd_pipe **pipe) in usbd_open_pipe()
184 u_int8_t flags, struct usbd_pipe **pipe, int ival) in usbd_open_pipe_ival()
215 u_int8_t flags, struct usbd_pipe **pipe, void *priv, in usbd_open_pipe_intr()
254 usbd_close_pipe(struct usbd_pipe *pipe) in usbd_close_pipe()
280 struct usbd_pipe *pipe = xfer->pipe; in usbd_transfer() local
438 usbd_setup_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe, in usbd_setup_xfer()
475 usbd_setup_isoc_xfer(struct usbd_xfer *xfer, struct usbd_pipe *pipe, in usbd_setup_isoc_xfer()
550 usbd_abort_pipe(struct usbd_pipe *pipe) in usbd_abort_pipe()
[all …]
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| /openbsd/src/sys/dev/pci/drm/i915/gvt/ |
| D | display.c | 49 int pipe = -1; in get_edp_pipe() local
78 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled()
181 int pipe; in emulate_monitor_status_change() local
629 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) in emulate_vblank_on_pipe()
660 int pipe; in intel_vgpu_emulate_vblank() local
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