| /netbsd/src/external/gpl3/gdb/dist/sim/mips/ |
| D | sim-main.c | 53 sim_cpu *CPU, in load_memory()
170 sim_cpu *CPU, in store_memory()
259 sim_cpu *CPU, in ifetch32()
283 sim_cpu *CPU, in ifetch16()
325 sim_cpu *CPU, in cache_op()
403 sim_cpu *CPU, in pending_tick()
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| D | m16run.c | 31 #define CPU cpu macro
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| D | micromipsrun.c | 41 #define CPU cpu macro
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| D | dv-tx3904cpu.c | 148 #define CPU cpu in deliver_tx3904cpu_interrupt() macro
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| /netbsd/src/external/gpl3/gdb/dist/opcodes/ |
| D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| D | arc-ext.h | 81 #define INSERT_XOP(OP, NAME, CODE, MASK, CPU, ARG, FLG) \ argument
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| /netbsd/src/external/gpl3/binutils/dist/opcodes/ |
| D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| D | arc-ext.h | 81 #define INSERT_XOP(OP, NAME, CODE, MASK, CPU, ARG, FLG) \ argument
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/ |
| D | vxworks.h | 67 #define VX_CPUDEF(CPU) builtin_define(VX_CPU_PREFIX "CPU=" #CPU) argument
68 #define VX_CPUVDEF(CPU) builtin_define(VX_CPU_PREFIX "CPU_VARIANT=" #CPU) argument
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| D | default64.h | 21 #define RS6000_CPU(NAME, CPU, FLAGS) argument
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| D | vxworks.h | 110 #define VX_MCPU(CPU,CPUID) \ argument
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| D | aix73.h | 136 #define RS6000_CPU(NAME, CPU, FLAGS) argument
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| D | aix72.h | 135 #define RS6000_CPU(NAME, CPU, FLAGS) argument
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| D | aix71.h | 134 #define RS6000_CPU(NAME, CPU, FLAGS) argument
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| D | driver-rs6000.cc | 47 #define RS6000_CPU(NAME, CPU, FLAGS) NAME, argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/m32r/ |
| D | sim-main.h | 25 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/mn10300/ |
| D | sim-main.h | 29 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
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| D | mn10300-sim.h | 44 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA) argument
45 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC) argument
46 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC) argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/lm32/ |
| D | sim-main.h | 55 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
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| /netbsd/src/external/cddl/osnet/sys/sys/ |
| D | proc.h | 72 #define CPU curcpu() macro
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| /netbsd/src/external/gpl3/gdb/dist/sim/iq2000/ |
| D | sim-main.h | 41 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/microblaze/ |
| D | microblaze.h | 27 #define CPU (*MICROBLAZE_SIM_CPU (cpu)) macro
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| /netbsd/src/external/gpl3/gdb/dist/sim/common/ |
| D | cgen-cpu.h | 108 #define CPU(x) (CPU_CGEN_HW (current_cpu)->x) macro
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| /netbsd/src/external/gpl3/gdb/dist/sim/frv/ |
| D | sim-main.h | 106 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/cris/ |
| D | cris-sim.h | 101 #define cris_trace_printf(SD, CPU, FMT...) \ argument
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