Lines Matching defs:mlx4_caps
430 struct mlx4_caps { struct
431 u64 fw_ver;
432 u32 function;
433 int num_ports;
434 int vl_cap[MLX4_MAX_PORTS + 1];
435 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
436 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
437 u64 def_mac[MLX4_MAX_PORTS + 1];
438 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
439 int gid_table_len[MLX4_MAX_PORTS + 1];
440 int pkey_table_len[MLX4_MAX_PORTS + 1];
441 int trans_type[MLX4_MAX_PORTS + 1];
442 int vendor_oui[MLX4_MAX_PORTS + 1];
443 int wavelength[MLX4_MAX_PORTS + 1];
444 u64 trans_code[MLX4_MAX_PORTS + 1];
445 int local_ca_ack_delay;
446 int num_uars;
447 u32 uar_page_size;
448 int bf_reg_size;
449 int bf_regs_per_page;
450 int max_sq_sg;
451 int max_rq_sg;
452 int num_qps;
453 int max_wqes;
454 int max_sq_desc_sz;
455 int max_rq_desc_sz;
456 int max_qp_init_rdma;
457 int max_qp_dest_rdma;
458 u32 *qp0_proxy;
459 u32 *qp1_proxy;
460 u32 *qp0_tunnel;
461 u32 *qp1_tunnel;
462 int num_srqs;
463 int max_srq_wqes;
464 int max_srq_sge;
465 int reserved_srqs;
466 int num_cqs;
467 int max_cqes;
468 int reserved_cqs;
469 int num_eqs;
470 int reserved_eqs;
471 int num_comp_vectors;
472 int comp_pool;
473 int num_mpts;
474 int max_fmr_maps;
475 u64 num_mtts;
476 int fmr_reserved_mtts;
477 int reserved_mtts;
478 int reserved_mrws;
479 int reserved_uars;
480 int num_mgms;
481 int num_amgms;
482 int reserved_mcgs;
483 int num_qp_per_mgm;
484 int steering_mode;
485 int num_pds;
486 int reserved_pds;
487 int max_xrcds;
488 int reserved_xrcds;
489 int mtt_entry_sz;
490 u32 max_msg_sz;
491 u32 page_size_cap;
492 u64 flags;
493 u64 flags2;
494 u32 bmme_flags;
495 u32 reserved_lkey;
496 u16 stat_rate_support;
497 u8 cq_timestamp;
498 u8 port_width_cap[MLX4_MAX_PORTS + 1];
499 int max_gso_sz;
500 int max_rss_tbl_sz;
501 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
502 int reserved_qps;
503 int reserved_qps_base[MLX4_NUM_QP_REGION];
504 int log_num_macs;
505 int log_num_vlans;
506 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
507 u8 supported_type[MLX4_MAX_PORTS + 1];
508 u8 suggested_type[MLX4_MAX_PORTS + 1];
509 u8 default_sense[MLX4_MAX_PORTS + 1];
510 u32 port_mask[MLX4_MAX_PORTS + 1];
511 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
512 u32 max_counters;
513 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
514 u16 sqp_demux;
515 u32 sync_qp;
516 u32 cq_flags;
517 u32 eqe_size;
518 u32 cqe_size;
519 u8 eqe_factor;
520 u32 userspace_caps; /* userspace must be aware to */
521 u32 function_caps; /* functions must be aware to */
522 u8 fast_drop;
523 u16 hca_core_clock;
524 u32 max_basic_counters;
525 u32 max_extended_counters;
526 u8 def_counter_index[MLX4_MAX_PORTS + 1];