Lines Matching refs:MLX4_MAX_PORTS

466 	u16 mtu[MLX4_MAX_PORTS + 1];
467 	__be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
469 	struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
470 	struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
479 	enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
496 	struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
505 	struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
517 		int res_port_rsvd[MLX4_MAX_PORTS];
521 		int res_port_free[MLX4_MAX_PORTS];
556 	struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
557 	int			init_port_ref[MLX4_MAX_PORTS + 1];
558 	u16			max_mtu[MLX4_MAX_PORTS + 1];
559 	int			disable_mcast_ref[MLX4_MAX_PORTS + 1];
773 	u8			do_sense_port[MLX4_MAX_PORTS + 1];
774 	u8			sense_allowed[MLX4_MAX_PORTS + 1];
804 	struct list_head	global_port_list[MLX4_MAX_PORTS];
805 	struct list_head	vf_list[MLX4_MAX_NUM_VF][MLX4_MAX_PORTS];
847 	struct mlx4_port_info	port[MLX4_MAX_PORTS + 1];
858 	u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
860 	struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128];