Lines Matching refs:interface
89 #define SPI4000_TWSI_ID(interface) (0x66 + interface) argument
125 static void __cvmx_spi4000_write(int interface, int address, uint32_t data) in __cvmx_spi4000_write() argument
128 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address); in __cvmx_spi4000_write()
129 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data); in __cvmx_spi4000_write()
131 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_WRITE); in __cvmx_spi4000_write()
133 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_WRITE_STATUS); in __cvmx_spi4000_write()
149 static uint32_t __cvmx_spi4000_read(int interface, int address) in __cvmx_spi4000_read() argument
154 cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_ADDRESS_HIGH, 2, 1, address); in __cvmx_spi4000_read()
156 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_READ); in __cvmx_spi4000_read()
158 status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_READ_STATUS); in __cvmx_spi4000_read()
166 status = cvmx_twsix_read_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_DATA0, 4, 1, &data); in __cvmx_spi4000_read()
186 static void __cvmx_spi4000_mdio_write(int interface, int port, int location, int val) in __cvmx_spi4000_mdio_write() argument
202 __cvmx_spi4000_write(interface, 0x0681, val); in __cvmx_spi4000_mdio_write()
205 __cvmx_spi4000_write(interface, 0x0680, mdio.u32); in __cvmx_spi4000_mdio_write()
218 static int __cvmx_spi4000_mdio_read(int interface, int port, int location) in __cvmx_spi4000_mdio_read() argument
227 __cvmx_spi4000_write(interface, 0x0680, mdio.u32); in __cvmx_spi4000_mdio_read()
231 mdio.u32 = __cvmx_spi4000_read(interface, 0x0680); in __cvmx_spi4000_mdio_read()
234 return __cvmx_spi4000_read(interface, 0x0681) >> 16; in __cvmx_spi4000_mdio_read()
242 static void __cvmx_spi4000_configure_mac(int interface) in __cvmx_spi4000_configure_mac() argument
251 __cvmx_spi4000_write(interface, 0x0505, 0x3ff); // reset all the MACs in __cvmx_spi4000_configure_mac()
252 __cvmx_spi4000_write(interface, 0x0620, 0x3ff); // reset the TX FIFOs in __cvmx_spi4000_configure_mac()
257 __cvmx_spi4000_write(interface, 0x059e, 0x3ff); // reset the RX FIFOs in __cvmx_spi4000_configure_mac()
261 __cvmx_spi4000_write(interface, 0x0505, 0x0); // reset all the MACs in __cvmx_spi4000_configure_mac()
265 __cvmx_spi4000_write(interface, 0x0500, 0x0); // disable all ports in __cvmx_spi4000_configure_mac()
281 __cvmx_spi4000_write(interface, port_offset | 0x0010, 0x3); in __cvmx_spi4000_configure_mac()
284 __cvmx_spi4000_write(interface, port_offset | 0x000f, 0x3fff); in __cvmx_spi4000_configure_mac()
302 __cvmx_spi4000_write(interface, port_offset | 0x0000, 0x0000); in __cvmx_spi4000_configure_mac()
304 __cvmx_spi4000_write(interface, port_offset | 0x0001, 0x0000); in __cvmx_spi4000_configure_mac()
318 __cvmx_spi4000_write(interface, port_offset | 0x0012, 0); in __cvmx_spi4000_configure_mac()
320 __cvmx_spi4000_write(interface, port_offset | 0x0012, 0x7); in __cvmx_spi4000_configure_mac()
323 __cvmx_spi4000_write(interface, port_offset | 0x0015, 0x1); in __cvmx_spi4000_configure_mac()
326 __cvmx_spi4000_write(interface, port_offset | 0x0018, 0x11cd); //?? in __cvmx_spi4000_configure_mac()
329 __cvmx_spi4000_write(interface, port_offset | 0x0019, 0x00); in __cvmx_spi4000_configure_mac()
333 __cvmx_spi4000_write(interface, 0x059f, 0x03ff); in __cvmx_spi4000_configure_mac()
338 __cvmx_spi4000_write(interface, port + 0x0600, 0x0900); // TXFIFO High watermark in __cvmx_spi4000_configure_mac()
339 __cvmx_spi4000_write(interface, port + 0x060a, 0x0800); // TXFIFO Low watermark in __cvmx_spi4000_configure_mac()
340 __cvmx_spi4000_write(interface, port + 0x0614, 0x0380); // TXFIFO threshold in __cvmx_spi4000_configure_mac()
344 __cvmx_spi4000_write(interface, 0x059e, 0x0); // reset the RX FIFOs in __cvmx_spi4000_configure_mac()
347 __cvmx_spi4000_write(interface, 0x0620, 0x0); // reset the TX FIFOs in __cvmx_spi4000_configure_mac()
351 __cvmx_spi4000_write(interface, 0x0500, 0x03ff); // enable all ports in __cvmx_spi4000_configure_mac()
362 static void __cvmx_spi4000_configure_phy(int interface) in __cvmx_spi4000_configure_phy() argument
374 cvmx_spi4000_check_speed(interface, port); in __cvmx_spi4000_configure_phy()
377 __cvmx_spi4000_mdio_write(interface, port, 0x14, 0x00e2); in __cvmx_spi4000_configure_phy()
380 __cvmx_spi4000_mdio_write(interface, port, 0x4, 0x0d01); in __cvmx_spi4000_configure_phy()
383 __cvmx_spi4000_mdio_write(interface, port, 0x0, 0x9140); in __cvmx_spi4000_configure_phy()
394 cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port) in cvmx_spi4000_check_speed() argument
402 if (!interface_is_spi4000[interface]) in cvmx_spi4000_check_speed()
450 read_status = __cvmx_spi4000_mdio_read(interface, port, 0x11); in cvmx_spi4000_check_speed()
462 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */ in cvmx_spi4000_check_speed()
464 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x1); /* 100Mbps */ in cvmx_spi4000_check_speed()
469 __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */ in cvmx_spi4000_check_speed()
502 int cvmx_spi4000_is_present(int interface) in cvmx_spi4000_is_present() argument
508 if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 0)) in cvmx_spi4000_is_present()
510 if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_LOW, 0)) in cvmx_spi4000_is_present()
512 interface_is_spi4000[interface] = 1; in cvmx_spi4000_is_present()
522 int cvmx_spi4000_initialize(int interface) in cvmx_spi4000_initialize() argument
524 if (!cvmx_spi4000_is_present(interface)) in cvmx_spi4000_initialize()
527 __cvmx_spi4000_configure_mac(interface); in cvmx_spi4000_initialize()
528 __cvmx_spi4000_configure_phy(interface); in cvmx_spi4000_initialize()