Lines Matching refs:Entry
152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
157 const ReduceEntry &Entry);
160 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
165 const ReduceEntry &Entry, bool LiveCPSR,
171 const ReduceEntry &Entry, bool LiveCPSR,
293 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, in VerifyPredAndCC() argument
296 if ((is2Addr && Entry.PredCC2 == 0) || in VerifyPredAndCC()
297 (!is2Addr && Entry.PredCC1 == 0)) { in VerifyPredAndCC()
316 } else if ((is2Addr && Entry.PredCC2 == 2) || in VerifyPredAndCC()
317 (!is2Addr && Entry.PredCC1 == 2)) { in VerifyPredAndCC()
368 const ReduceEntry &Entry) { in ReduceLoadStore() argument
377 unsigned Opc = Entry.NarrowOpc1; in ReduceLoadStore()
379 uint8_t ImmLimit = Entry.Imm1Limit; in ReduceLoadStore()
381 switch (Entry.WideOpc) { in ReduceLoadStore()
387 Opc = Entry.NarrowOpc2; in ReduceLoadStore()
388 ImmLimit = Entry.Imm2Limit; in ReduceLoadStore()
421 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) in ReduceLoadStore()
445 Opc = Entry.NarrowOpc2; // tPOP_RET in ReduceLoadStore()
458 (Entry.WideOpc == ARM::t2LDMIA_UPD || in ReduceLoadStore()
459 Entry.WideOpc == ARM::t2STMDB_UPD)) { in ReduceLoadStore()
460 Opc = Entry.NarrowOpc2; // tPOP or tPUSH in ReduceLoadStore()
463 (Entry.WideOpc != ARM::t2LDMIA_UPD && in ReduceLoadStore()
464 Entry.WideOpc != ARM::t2STMIA_UPD)) { in ReduceLoadStore()
529 const ReduceEntry &Entry, in ReduceSpecial() argument
536 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) in ReduceSpecial()
538 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceSpecial()
573 if (Entry.LowRegs1 && !VerifyLowRegs(MI)) in ReduceSpecial()
577 return ReduceLoadStore(MBB, MI, Entry); in ReduceSpecial()
588 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) in ReduceSpecial()
593 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceSpecial()
605 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceSpecial()
611 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceSpecial()
623 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceSpecial()
631 const ReduceEntry &Entry, in ReduceTo2Addr() argument
637 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs && in ReduceTo2Addr()
672 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
674 if (Entry.Imm2Limit) { in ReduceTo2Addr()
676 unsigned Limit = (1 << Entry.Imm2Limit) - 1; in ReduceTo2Addr()
681 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
686 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); in ReduceTo2Addr()
707 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead)) in ReduceTo2Addr()
712 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && in ReduceTo2Addr()
749 const ReduceEntry &Entry, in ReduceToNarrow() argument
754 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs && in ReduceToNarrow()
761 if (Entry.Imm1Limit) in ReduceToNarrow()
762 Limit = (1 << Entry.Imm1Limit) - 1; in ReduceToNarrow()
773 if (Entry.LowRegs1 && !isARMLowRegister(Reg)) in ReduceToNarrow()
783 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); in ReduceToNarrow()
803 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead)) in ReduceToNarrow()
808 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && in ReduceToNarrow()
899 const ReduceEntry &Entry = ReduceTable[OPI->second]; in ReduceMI() local
902 if (Entry.Special) in ReduceMI()
903 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop); in ReduceMI()
906 if (Entry.NarrowOpc2 && in ReduceMI()
907 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) in ReduceMI()
911 if (Entry.NarrowOpc1 && in ReduceMI()
912 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop)) in ReduceMI()