Lines Matching refs:N0
4006 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts() local
4007 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0); in getCTPOP16BitCounts()
4066 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements() local
4067 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0); in lowerCTPOP32BitElements()
5675 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
5677 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
5678 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
5686 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
5688 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
5689 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
5700 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
5704 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
5709 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
5716 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
5719 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
5723 std::swap(N0, N1); in LowerMUL()
5744 Op0 = SkipExtensionForVMULL(N0, DAG); in LowerMUL()
5759 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
5760 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
5762 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
5799 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i16() argument
5804 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
5806 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
5822 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
5823 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
5826 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
5827 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
5830 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
5831 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
5832 return N0; in LowerSDIV_v4i16()
5841 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
5846 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
5849 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
5853 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
5858 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
5861 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
5862 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerSDIV()
5864 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
5865 return N0; in LowerSDIV()
5867 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
5876 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
5881 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
5884 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
5888 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
5893 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
5896 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
5897 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerUDIV()
5899 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
5901 N0); in LowerUDIV()
5902 return N0; in LowerUDIV()
5908 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
5910 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
5931 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
5932 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
5935 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
5936 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
5939 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
5940 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
5941 return N0; in LowerUDIV()
8185 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
8187 if (N0.getNode()->hasOneUse()) { in combineSelectAndUseCommutative()
8188 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); in combineSelectAndUseCommutative()
8193 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); in combineSelectAndUseCommutative()
8202 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADDL() argument
8209 || N0.getOpcode() != ISD::BUILD_VECTOR in AddCombineToVPADDL()
8225 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in AddCombineToVPADDL()
8227 SDValue Vec = N0->getOperand(0)->getOperand(0); in AddCombineToVPADDL()
8234 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { in AddCombineToVPADDL()
8235 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT in AddCombineToVPADDL()
8238 SDValue ExtVec0 = N0->getOperand(i); in AddCombineToVPADDL()
8444 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
8449 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); in PerformADDCombineWithOperands()
8454 if (N0.getNode()->hasOneUse()) { in PerformADDCombineWithOperands()
8455 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); in PerformADDCombineWithOperands()
8466 SDValue N0 = N->getOperand(0); in PerformADDCombine() local
8470 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); in PerformADDCombine()
8475 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
8482 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
8487 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); in PerformSUBCombine()
8516 SDValue N0 = N->getOperand(0); in PerformVMULCombine() local
8518 unsigned Opcode = N0.getOpcode(); in PerformVMULCombine()
8525 std::swap(N0, N1); in PerformVMULCombine()
8528 if (N0 == N1) in PerformVMULCombine()
8533 SDValue N00 = N0->getOperand(0); in PerformVMULCombine()
8534 SDValue N01 = N0->getOperand(1); in PerformVMULCombine()
8710 SDValue N0 = N->getOperand(0); in PerformORCombine() local
8711 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) in PerformORCombine()
8723 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); in PerformORCombine()
8739 N0->getOperand(1), in PerformORCombine()
8740 N0->getOperand(0), in PerformORCombine()
8769 SDValue N00 = N0.getOperand(0); in PerformORCombine()
8774 SDValue MaskOp = N0.getOperand(1); in PerformORCombine()
9616 SDValue N0 = Op->getOperand(0); in PerformVCVTCombine() local
9638 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, in PerformVCVTCombine()
9921 SDValue N0 = N->getOperand(0); in PerformShiftCombine() local
9922 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP && in PerformShiftCombine()
9923 DAG.MaskedValueIsZero(N0.getOperand(0), in PerformShiftCombine()
9925 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1); in PerformShiftCombine()
9962 SDValue N0 = N->getOperand(0); in PerformExtendCombine() local
9968 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
9969 SDValue Vec = N0.getOperand(0); in PerformExtendCombine()
9970 SDValue Lane = N0.getOperand(1); in PerformExtendCombine()
9972 EVT EltVT = N0.getValueType(); in PerformExtendCombine()