Lines Matching refs:sc
167 struct rge_softc *sc = (struct rge_softc *)self; in rge_attach() local
185 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle, in rge_attach()
186 NULL, &sc->rge_bsize, 0)) { in rge_attach()
188 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag, in rge_attach()
189 &sc->rge_bhandle, NULL, &sc->rge_bsize, 0)) { in rge_attach()
191 0, &sc->rge_btag, &sc->rge_bhandle, NULL, in rge_attach()
192 &sc->rge_bsize, 0)) { in rge_attach()
204 q->q_sc = sc; in rge_attach()
207 sc->sc_queues = q; in rge_attach()
208 sc->sc_nqueues = 1; in rge_attach()
215 sc->rge_flags |= RGE_FLAG_MSI; in rge_attach()
221 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, rge_intr, in rge_attach()
222 sc, sc->sc_dev.dv_xname); in rge_attach()
223 if (sc->sc_ih == NULL) { in rge_attach()
232 sc->sc_dmat = pa->pa_dmat; in rge_attach()
233 sc->sc_pc = pa->pa_pc; in rge_attach()
234 sc->sc_tag = pa->pa_tag; in rge_attach()
237 hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV; in rge_attach()
240 sc->rge_type = MAC_CFG3; in rge_attach()
243 sc->rge_type = MAC_CFG5; in rge_attach()
246 sc->rge_type = MAC_CFG2_8126; in rge_attach()
253 rge_config_imtype(sc, RGE_IMTYPE_SIM); in rge_attach()
269 rge_chipinit(sc); in rge_attach()
271 rge_get_macaddr(sc, eaddr); in rge_attach()
274 memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN); in rge_attach()
276 if (rge_allocmem(sc)) in rge_attach()
279 ifp = &sc->sc_arpcom.ac_if; in rge_attach()
280 ifp->if_softc = sc; in rge_attach()
281 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); in rge_attach()
302 timeout_set(&sc->sc_timeout, rge_tick, sc); in rge_attach()
303 task_set(&sc->sc_task, rge_txstart, sc); in rge_attach()
306 ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd, in rge_attach()
308 rge_add_media_types(sc); in rge_attach()
309 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); in rge_attach()
310 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); in rge_attach()
311 sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media; in rge_attach()
317 rge_kstat_attach(sc); in rge_attach()
325 struct rge_softc *sc = (struct rge_softc *)self; in rge_activate() local
331 rge_wol_power(sc); in rge_activate()
341 struct rge_softc *sc = arg; in rge_intr() local
342 struct rge_queues *q = sc->sc_queues; in rge_intr()
343 struct ifnet *ifp = &sc->sc_arpcom.ac_if; in rge_intr()
351 RGE_WRITE_4(sc, RGE_IMR, 0); in rge_intr()
353 if (!(sc->rge_flags & RGE_FLAG_MSI)) { in rge_intr()
354 if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0) in rge_intr()
358 status = RGE_READ_4(sc, RGE_ISR); in rge_intr()
360 RGE_WRITE_4(sc, RGE_ISR, status); in rge_intr()
366 if (status & sc->rge_intrs) { in rge_intr()
378 if (sc->rge_timerintr) { in rge_intr()
384 rge_setup_intr(sc, RGE_IMTYPE_NONE); in rge_intr()
394 RGE_WRITE_4(sc, RGE_TIMERCNT, 1); in rge_intr()
401 rge_setup_intr(sc, RGE_IMTYPE_SIM); in rge_intr()
404 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); in rge_intr()
410 rge_tx_list_sync(struct rge_softc *sc, struct rge_queues *q, in rge_tx_list_sync() argument
413 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, in rge_tx_list_sync()
421 struct rge_softc *sc = q->q_sc; in rge_encap() local
434 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT); in rge_encap()
440 bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, in rge_encap()
455 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, in rge_encap()
514 rge_tx_list_sync(sc, q, idx, txmap->dm_nsegs, in rge_encap()
517 rge_tx_list_sync(sc, q, idx, RGE_TX_LIST_CNT - idx, in rge_encap()
519 rge_tx_list_sync(sc, q, 0, cur + 1, in rge_encap()
525 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_POSTWRITE); in rge_encap()
527 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_PREWRITE); in rge_encap()
535 struct rge_softc *sc = ifp->if_softc; in rge_ioctl() local
560 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); in rge_ioctl()
564 NULL, MCLBYTES, &sc->sc_queues->q_rx.rge_rx_ring); in rge_ioctl()
567 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); in rge_ioctl()
572 rge_iff(sc); in rge_ioctl()
584 struct rge_softc *sc = ifp->if_softc; in rge_start() local
585 struct rge_queues *q = sc->sc_queues; in rge_start()
635 ifq_serialize(ifq, &sc->sc_task); in rge_start()
641 struct rge_softc *sc = ifp->if_softc; in rge_watchdog() local
643 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); in rge_watchdog()
652 struct rge_softc *sc = ifp->if_softc; in rge_init() local
653 struct rge_queues *q = sc->sc_queues; in rge_init()
660 rge_set_macaddr(sc, sc->sc_arpcom.ac_enaddr); in rge_init()
666 rge_chipinit(sc); in rge_init()
668 if (rge_phy_config(sc)) in rge_init()
671 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_init()
673 RGE_CLRBIT_1(sc, 0xf1, 0x80); in rge_init()
674 rge_disable_aspm_clkreq(sc); in rge_init()
675 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, in rge_init()
679 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, in rge_init()
681 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, in rge_init()
683 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, in rge_init()
685 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, in rge_init()
689 if (sc->rge_type == MAC_CFG3) in rge_init()
691 else if (sc->rge_type == MAC_CFG5) in rge_init()
695 RGE_WRITE_4(sc, RGE_RXCFG, rxconf); in rge_init()
696 RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG); in rge_init()
698 val = rge_read_csi(sc, 0x70c) & ~0xff000000; in rge_init()
699 rge_write_csi(sc, 0x70c, val | 0x27000000); in rge_init()
701 if (sc->rge_type == MAC_CFG2_8126) { in rge_init()
703 val = rge_read_csi(sc, 0x890) & ~0x00000001; in rge_init()
704 rge_write_csi(sc, 0x890, val); in rge_init()
706 RGE_WRITE_2(sc, 0x0382, 0x221b); in rge_init()
708 RGE_WRITE_1(sc, RGE_RSS_CTRL, 0); in rge_init()
710 val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c; in rge_init()
711 RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2); in rge_init()
713 RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN); in rge_init()
715 rge_write_mac_ocp(sc, 0xc140, 0xffff); in rge_init()
716 rge_write_mac_ocp(sc, 0xc142, 0xffff); in rge_init()
718 RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); in rge_init()
720 if (sc->rge_type == MAC_CFG2_8126) in rge_init()
721 RGE_CLRBIT_1(sc, 0xd8, 0x02); in rge_init()
723 val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700; in rge_init()
724 if (sc->rge_type == MAC_CFG3) in rge_init()
725 rge_write_mac_ocp(sc, 0xe614, val | 0x0300); in rge_init()
726 else if (sc->rge_type == MAC_CFG5) in rge_init()
727 rge_write_mac_ocp(sc, 0xe614, val | 0x0200); in rge_init()
729 rge_write_mac_ocp(sc, 0xe614, val | 0x0400); in rge_init()
731 val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00; in rge_init()
732 rge_write_mac_ocp(sc, 0xe63e, val | in rge_init()
733 ((fls(sc->sc_nqueues) - 1) & 0x03) << 10); in rge_init()
735 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030); in rge_init()
736 if (sc->rge_type != MAC_CFG5) in rge_init()
737 RGE_MAC_SETBIT(sc, 0xe63e, 0x0020); in rge_init()
739 RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001); in rge_init()
740 RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001); in rge_init()
742 RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c); in rge_init()
744 val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff; in rge_init()
745 rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033); in rge_init()
747 val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0; in rge_init()
748 rge_write_mac_ocp(sc, 0xeb50, val | 0x0040); in rge_init()
750 RGE_MAC_CLRBIT(sc, 0xe056, 0x00f0); in rge_init()
752 RGE_WRITE_1(sc, RGE_TDFNR, 0x10); in rge_init()
754 RGE_MAC_CLRBIT(sc, 0xe040, 0x1000); in rge_init()
756 val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003; in rge_init()
757 rge_write_mac_ocp(sc, 0xea1c, val | 0x0001); in rge_init()
759 rge_write_mac_ocp(sc, 0xe0c0, 0x4000); in rge_init()
761 RGE_MAC_SETBIT(sc, 0xe052, 0x0060); in rge_init()
762 RGE_MAC_CLRBIT(sc, 0xe052, 0x0088); in rge_init()
764 val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff; in rge_init()
765 rge_write_mac_ocp(sc, 0xd430, val | 0x045f); in rge_init()
767 RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN); in rge_init()
769 if (sc->rge_type == MAC_CFG3) in rge_init()
770 RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01); in rge_init()
773 RGE_MAC_CLRBIT(sc, 0xe080, 0x0002); in rge_init()
775 if (sc->rge_type == MAC_CFG2_8126) in rge_init()
776 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304); in rge_init()
778 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004); in rge_init()
780 RGE_MAC_SETBIT(sc, 0xeb54, 0x0001); in rge_init()
782 RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001); in rge_init()
784 RGE_CLRBIT_2(sc, 0x1880, 0x0030); in rge_init()
787 if (sc->rge_type != MAC_CFG3) in rge_init()
788 RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN); in rge_init()
791 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); in rge_init()
792 RGE_WRITE_4(sc, RGE_TIMERINT1, 0); in rge_init()
793 RGE_WRITE_4(sc, RGE_TIMERINT2, 0); in rge_init()
794 RGE_WRITE_4(sc, RGE_TIMERINT3, 0); in rge_init()
796 num_miti = (sc->rge_type == MAC_CFG3) ? 64 : 32; in rge_init()
799 RGE_WRITE_4(sc, RGE_INTMITI(i), 0); in rge_init()
801 if (sc->rge_type == MAC_CFG5) { in rge_init()
802 RGE_CLRBIT_1(sc, RGE_INT_CFG0, in rge_init()
805 RGE_WRITE_2(sc, RGE_INT_CFG1, 0); in rge_init()
808 RGE_MAC_SETBIT(sc, 0xc0ac, 0x1f80); in rge_init()
810 rge_write_mac_ocp(sc, 0xe098, 0xc302); in rge_init()
812 RGE_MAC_CLRBIT(sc, 0xe032, 0x0003); in rge_init()
813 val = rge_read_csi(sc, 0x98) & ~0x0000ff00; in rge_init()
814 rge_write_csi(sc, 0x98, val); in rge_init()
816 val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff; in rge_init()
817 rge_write_mac_ocp(sc, 0xe092, val); in rge_init()
820 RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); in rge_init()
822 RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM); in rge_init()
825 RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); in rge_init()
828 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); in rge_init()
832 rge_iff(sc); in rge_init()
834 rge_disable_aspm_clkreq(sc); in rge_init()
836 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_init()
842 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); in rge_init()
845 rge_setup_intr(sc, RGE_IMTYPE_SIM); in rge_init()
850 timeout_add_sec(&sc->sc_timeout, 1); in rge_init()
859 struct rge_softc *sc = ifp->if_softc; in rge_stop() local
860 struct rge_queues *q = sc->sc_queues; in rge_stop()
863 timeout_del(&sc->sc_timeout); in rge_stop()
867 sc->rge_timerintr = 0; in rge_stop()
869 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | in rge_stop()
873 rge_hw_reset(sc); in rge_stop()
875 RGE_MAC_CLRBIT(sc, 0xc0ac, 0x1f80); in rge_stop()
877 intr_barrier(sc->sc_ih); in rge_stop()
890 bus_dmamap_unload(sc->sc_dmat, in rge_stop()
900 bus_dmamap_unload(sc->sc_dmat, in rge_stop()
914 struct rge_softc *sc = ifp->if_softc; in rge_ifmedia_upd() local
915 struct ifmedia *ifm = &sc->sc_media; in rge_ifmedia_upd()
922 RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); in rge_ifmedia_upd()
923 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); in rge_ifmedia_upd()
924 if (sc->rge_type == MAC_CFG2_8126) in rge_ifmedia_upd()
925 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0002); in rge_ifmedia_upd()
927 val = rge_read_phy_ocp(sc, 0xa5d4); in rge_ifmedia_upd()
929 if (sc->rge_type == MAC_CFG2_8126) in rge_ifmedia_upd()
937 val |= (sc->rge_type != MAC_CFG2_8126) ? in rge_ifmedia_upd()
952 gig = rge_read_phy(sc, 0, MII_100T2CR) & in rge_ifmedia_upd()
960 gig = rge_read_phy(sc, 0, MII_100T2CR) & in rge_ifmedia_upd()
967 printf("%s: unsupported media type\n", sc->sc_dev.dv_xname); in rge_ifmedia_upd()
971 rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC); in rge_ifmedia_upd()
972 rge_write_phy(sc, 0, MII_100T2CR, gig); in rge_ifmedia_upd()
973 rge_write_phy_ocp(sc, 0xa5d4, val); in rge_ifmedia_upd()
974 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | in rge_ifmedia_upd()
986 struct rge_softc *sc = ifp->if_softc; in rge_ifmedia_sts() local
992 if (rge_get_link_status(sc)) { in rge_ifmedia_sts()
995 status = RGE_READ_2(sc, RGE_PHYSTAT); in rge_ifmedia_sts()
1019 rge_allocmem(struct rge_softc *sc) in rge_allocmem() argument
1021 struct rge_queues *q = sc->sc_queues; in rge_allocmem()
1025 error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1, in rge_allocmem()
1029 printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname); in rge_allocmem()
1032 error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0, in rge_allocmem()
1036 printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname); in rge_allocmem()
1041 error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg, in rge_allocmem()
1045 printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname); in rge_allocmem()
1046 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, in rge_allocmem()
1050 error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map, in rge_allocmem()
1053 printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname); in rge_allocmem()
1054 bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); in rge_allocmem()
1055 bus_dmamem_unmap(sc->sc_dmat, in rge_allocmem()
1057 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, in rge_allocmem()
1064 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, in rge_allocmem()
1070 sc->sc_dev.dv_xname); in rge_allocmem()
1076 error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1, in rge_allocmem()
1080 printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname); in rge_allocmem()
1083 error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0, in rge_allocmem()
1087 printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname); in rge_allocmem()
1092 error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg, in rge_allocmem()
1096 printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname); in rge_allocmem()
1097 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, in rge_allocmem()
1101 error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_allocmem()
1104 printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname); in rge_allocmem()
1105 bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); in rge_allocmem()
1106 bus_dmamem_unmap(sc->sc_dmat, in rge_allocmem()
1108 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, in rge_allocmem()
1115 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1, in rge_allocmem()
1120 sc->sc_dev.dv_xname); in rge_allocmem()
1134 struct rge_softc *sc = q->q_sc; in rge_newbuf() local
1153 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) { in rge_newbuf()
1158 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, in rge_newbuf()
1174 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_newbuf()
1178 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_newbuf()
1183 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_newbuf()
1221 struct rge_softc *sc = q->q_sc; in rge_tx_list_init() local
1233 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0, in rge_tx_list_init()
1243 struct rge_softc *sc = q->q_sc; in rge_rxeof() local
1246 struct ifnet *ifp = &sc->sc_arpcom.ac_if; in rge_rxeof()
1259 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_rxeof()
1264 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_rxeof()
1271 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0, in rge_rxeof()
1273 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap); in rge_rxeof()
1351 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_rxeof()
1355 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_rxeof()
1360 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, in rge_rxeof()
1378 struct rge_softc *sc = q->q_sc; in rge_txeof() local
1379 struct ifnet *ifp = &sc->sc_arpcom.ac_if; in rge_txeof()
1393 rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_POSTREAD); in rge_txeof()
1395 rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_PREREAD); in rge_txeof()
1401 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0, in rge_txeof()
1403 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); in rge_txeof()
1421 rge_tx_list_sync(sc, q, cons, idx - cons, in rge_txeof()
1424 rge_tx_list_sync(sc, q, cons, RGE_TX_LIST_CNT - cons, in rge_txeof()
1426 rge_tx_list_sync(sc, q, 0, idx, in rge_txeof()
1435 ifq_serialize(&ifp->if_snd, &sc->sc_task); in rge_txeof()
1443 rge_reset(struct rge_softc *sc) in rge_reset() argument
1447 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | in rge_reset()
1452 RGE_SETBIT_1(sc, RGE_PPSW, 0x08); in rge_reset()
1455 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ); in rge_reset()
1456 if (sc->rge_type != MAC_CFG2_8126) { in rge_reset()
1459 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ)) in rge_reset()
1466 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY | in rge_reset()
1471 if (sc->rge_type != MAC_CFG3) { in rge_reset()
1474 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103) in rge_reset()
1482 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); in rge_reset()
1486 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET)) in rge_reset()
1490 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); in rge_reset()
1494 rge_iff(struct rge_softc *sc) in rge_iff() argument
1496 struct ifnet *ifp = &sc->sc_arpcom.ac_if; in rge_iff()
1497 struct arpcom *ac = &sc->sc_arpcom; in rge_iff()
1504 rxfilt = RGE_READ_4(sc, RGE_RXCFG); in rge_iff()
1539 RGE_WRITE_4(sc, RGE_RXCFG, rxfilt); in rge_iff()
1540 RGE_WRITE_4(sc, RGE_MAR0, swap32(hashes[1])); in rge_iff()
1541 RGE_WRITE_4(sc, RGE_MAR4, swap32(hashes[0])); in rge_iff()
1545 rge_chipinit(struct rge_softc *sc) in rge_chipinit() argument
1547 rge_exit_oob(sc); in rge_chipinit()
1548 rge_set_phy_power(sc, 1); in rge_chipinit()
1549 rge_hw_init(sc); in rge_chipinit()
1550 rge_hw_reset(sc); in rge_chipinit()
1554 rge_set_phy_power(struct rge_softc *sc, int on) in rge_set_phy_power() argument
1559 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); in rge_set_phy_power()
1561 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN); in rge_set_phy_power()
1564 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) in rge_set_phy_power()
1569 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN); in rge_set_phy_power()
1570 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80); in rge_set_phy_power()
1571 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40); in rge_set_phy_power()
1576 rge_ephy_config(struct rge_softc *sc) in rge_ephy_config() argument
1578 switch (sc->rge_type) { in rge_ephy_config()
1580 rge_ephy_config_mac_cfg3(sc); in rge_ephy_config()
1583 rge_ephy_config_mac_cfg5(sc); in rge_ephy_config()
1591 rge_ephy_config_mac_cfg3(struct rge_softc *sc) in rge_ephy_config_mac_cfg3() argument
1597 rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg, in rge_ephy_config_mac_cfg3()
1600 val = rge_read_ephy(sc, 0x002a) & ~0x7000; in rge_ephy_config_mac_cfg3()
1601 rge_write_ephy(sc, 0x002a, val | 0x3000); in rge_ephy_config_mac_cfg3()
1602 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); in rge_ephy_config_mac_cfg3()
1603 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); in rge_ephy_config_mac_cfg3()
1604 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); in rge_ephy_config_mac_cfg3()
1605 rge_write_ephy(sc, 0x0002, 0x6042); in rge_ephy_config_mac_cfg3()
1606 rge_write_ephy(sc, 0x0006, 0x0014); in rge_ephy_config_mac_cfg3()
1607 val = rge_read_ephy(sc, 0x006a) & ~0x7000; in rge_ephy_config_mac_cfg3()
1608 rge_write_ephy(sc, 0x006a, val | 0x3000); in rge_ephy_config_mac_cfg3()
1609 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); in rge_ephy_config_mac_cfg3()
1610 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); in rge_ephy_config_mac_cfg3()
1611 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); in rge_ephy_config_mac_cfg3()
1612 rge_write_ephy(sc, 0x0042, 0x6042); in rge_ephy_config_mac_cfg3()
1613 rge_write_ephy(sc, 0x0046, 0x0014); in rge_ephy_config_mac_cfg3()
1617 rge_ephy_config_mac_cfg5(struct rge_softc *sc) in rge_ephy_config_mac_cfg5() argument
1622 rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg, in rge_ephy_config_mac_cfg5()
1627 rge_phy_config(struct rge_softc *sc) in rge_phy_config() argument
1631 rge_ephy_config(sc); in rge_phy_config()
1634 rge_write_phy(sc, 0, MII_ANAR, in rge_phy_config()
1635 rge_read_phy(sc, 0, MII_ANAR) & in rge_phy_config()
1637 rge_write_phy(sc, 0, MII_100T2CR, in rge_phy_config()
1638 rge_read_phy(sc, 0, MII_100T2CR) & in rge_phy_config()
1640 if (sc->rge_type == MAC_CFG2_8126) in rge_phy_config()
1641 RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX | RGE_ADV_5000TFDX); in rge_phy_config()
1643 RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX); in rge_phy_config()
1644 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | in rge_phy_config()
1647 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET)) in rge_phy_config()
1652 printf("%s: PHY reset failed\n", sc->sc_dev.dv_xname); in rge_phy_config()
1657 rge_write_phy_ocp(sc, 0xa436, 0x801e); in rge_phy_config()
1658 sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438); in rge_phy_config()
1660 switch (sc->rge_type) { in rge_phy_config()
1662 rge_phy_config_mac_cfg2_8126(sc); in rge_phy_config()
1665 rge_phy_config_mac_cfg3(sc); in rge_phy_config()
1668 rge_phy_config_mac_cfg5(sc); in rge_phy_config()
1674 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); in rge_phy_config()
1677 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); in rge_phy_config()
1678 if (sc->rge_type == MAC_CFG3) { in rge_phy_config()
1679 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); in rge_phy_config()
1680 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); in rge_phy_config()
1681 } else if (sc->rge_type == MAC_CFG5) in rge_phy_config()
1682 RGE_PHY_SETBIT(sc, 0xa432, 0x0010); in rge_phy_config()
1684 RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006); in rge_phy_config()
1685 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); in rge_phy_config()
1686 if (sc->rge_type == MAC_CFG2_8126) in rge_phy_config()
1687 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); in rge_phy_config()
1688 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); in rge_phy_config()
1689 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); in rge_phy_config()
1690 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); in rge_phy_config()
1693 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); in rge_phy_config()
1694 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); in rge_phy_config()
1695 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); in rge_phy_config()
1701 rge_phy_config_mac_cfg2_8126(struct rge_softc *sc) in rge_phy_config_mac_cfg2_8126() argument
1718 rge_phy_config_mcu(sc, RGE_MAC_CFG2_8126_MCODE_VER); in rge_phy_config_mac_cfg2_8126()
1720 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_cfg2_8126()
1721 rge_write_phy_ocp(sc, 0xa436, 0x80bf); in rge_phy_config_mac_cfg2_8126()
1722 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1723 rge_write_phy_ocp(sc, 0xa438, val | 0xed00); in rge_phy_config_mac_cfg2_8126()
1724 rge_write_phy_ocp(sc, 0xa436, 0x80cd); in rge_phy_config_mac_cfg2_8126()
1725 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1726 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); in rge_phy_config_mac_cfg2_8126()
1727 rge_write_phy_ocp(sc, 0xa436, 0x80d1); in rge_phy_config_mac_cfg2_8126()
1728 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1729 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); in rge_phy_config_mac_cfg2_8126()
1730 rge_write_phy_ocp(sc, 0xa436, 0x80d4); in rge_phy_config_mac_cfg2_8126()
1731 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1732 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); in rge_phy_config_mac_cfg2_8126()
1733 rge_write_phy_ocp(sc, 0xa436, 0x80e1); in rge_phy_config_mac_cfg2_8126()
1734 rge_write_phy_ocp(sc, 0xa438, 0x10cc); in rge_phy_config_mac_cfg2_8126()
1735 rge_write_phy_ocp(sc, 0xa436, 0x80e5); in rge_phy_config_mac_cfg2_8126()
1736 rge_write_phy_ocp(sc, 0xa438, 0x4f0c); in rge_phy_config_mac_cfg2_8126()
1737 rge_write_phy_ocp(sc, 0xa436, 0x8387); in rge_phy_config_mac_cfg2_8126()
1738 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1739 rge_write_phy_ocp(sc, 0xa438, val | 0x4700); in rge_phy_config_mac_cfg2_8126()
1740 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0; in rge_phy_config_mac_cfg2_8126()
1741 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080); in rge_phy_config_mac_cfg2_8126()
1742 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010); in rge_phy_config_mac_cfg2_8126()
1743 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000); in rge_phy_config_mac_cfg2_8126()
1744 rge_write_phy_ocp(sc, 0xb87c, 0x8321); in rge_phy_config_mac_cfg2_8126()
1745 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1746 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_cfg2_8126()
1747 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c); in rge_phy_config_mac_cfg2_8126()
1748 rge_write_phy_ocp(sc, 0xa436, 0x8183); in rge_phy_config_mac_cfg2_8126()
1749 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1750 rge_write_phy_ocp(sc, 0xa438, val | 0x5900); in rge_phy_config_mac_cfg2_8126()
1751 RGE_PHY_SETBIT(sc, 0xad94, 0x0020); in rge_phy_config_mac_cfg2_8126()
1752 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); in rge_phy_config_mac_cfg2_8126()
1753 RGE_PHY_SETBIT(sc, 0xb648, 0x4000); in rge_phy_config_mac_cfg2_8126()
1754 rge_write_phy_ocp(sc, 0xb87c, 0x839e); in rge_phy_config_mac_cfg2_8126()
1755 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1756 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00); in rge_phy_config_mac_cfg2_8126()
1757 rge_write_phy_ocp(sc, 0xb87c, 0x83f2); in rge_phy_config_mac_cfg2_8126()
1758 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1759 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_cfg2_8126()
1760 RGE_PHY_SETBIT(sc, 0xada0, 0x0002); in rge_phy_config_mac_cfg2_8126()
1761 rge_write_phy_ocp(sc, 0xb87c, 0x80f3); in rge_phy_config_mac_cfg2_8126()
1762 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1763 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900); in rge_phy_config_mac_cfg2_8126()
1764 rge_write_phy_ocp(sc, 0xb87c, 0x8126); in rge_phy_config_mac_cfg2_8126()
1765 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1766 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100); in rge_phy_config_mac_cfg2_8126()
1767 rge_write_phy_ocp(sc, 0xb87c, 0x893a); in rge_phy_config_mac_cfg2_8126()
1768 rge_write_phy_ocp(sc, 0xb87e, 0x8080); in rge_phy_config_mac_cfg2_8126()
1769 rge_write_phy_ocp(sc, 0xb87c, 0x8647); in rge_phy_config_mac_cfg2_8126()
1770 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1771 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); in rge_phy_config_mac_cfg2_8126()
1772 rge_write_phy_ocp(sc, 0xb87c, 0x862c); in rge_phy_config_mac_cfg2_8126()
1773 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1774 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200); in rge_phy_config_mac_cfg2_8126()
1775 rge_write_phy_ocp(sc, 0xb87c, 0x864a); in rge_phy_config_mac_cfg2_8126()
1776 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1777 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); in rge_phy_config_mac_cfg2_8126()
1778 rge_write_phy_ocp(sc, 0xb87c, 0x80a0); in rge_phy_config_mac_cfg2_8126()
1779 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); in rge_phy_config_mac_cfg2_8126()
1780 rge_write_phy_ocp(sc, 0xb87c, 0x805e); in rge_phy_config_mac_cfg2_8126()
1781 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); in rge_phy_config_mac_cfg2_8126()
1782 rge_write_phy_ocp(sc, 0xb87c, 0x8056); in rge_phy_config_mac_cfg2_8126()
1783 rge_write_phy_ocp(sc, 0xb87e, 0x3077); in rge_phy_config_mac_cfg2_8126()
1784 rge_write_phy_ocp(sc, 0xb87c, 0x8058); in rge_phy_config_mac_cfg2_8126()
1785 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1786 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); in rge_phy_config_mac_cfg2_8126()
1787 rge_write_phy_ocp(sc, 0xb87c, 0x8098); in rge_phy_config_mac_cfg2_8126()
1788 rge_write_phy_ocp(sc, 0xb87e, 0x3077); in rge_phy_config_mac_cfg2_8126()
1789 rge_write_phy_ocp(sc, 0xb87c, 0x809a); in rge_phy_config_mac_cfg2_8126()
1790 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1791 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); in rge_phy_config_mac_cfg2_8126()
1792 rge_write_phy_ocp(sc, 0xb87c, 0x8052); in rge_phy_config_mac_cfg2_8126()
1793 rge_write_phy_ocp(sc, 0xb87e, 0x3733); in rge_phy_config_mac_cfg2_8126()
1794 rge_write_phy_ocp(sc, 0xb87c, 0x8094); in rge_phy_config_mac_cfg2_8126()
1795 rge_write_phy_ocp(sc, 0xb87e, 0x3733); in rge_phy_config_mac_cfg2_8126()
1796 rge_write_phy_ocp(sc, 0xb87c, 0x807f); in rge_phy_config_mac_cfg2_8126()
1797 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); in rge_phy_config_mac_cfg2_8126()
1798 rge_write_phy_ocp(sc, 0xb87c, 0x803d); in rge_phy_config_mac_cfg2_8126()
1799 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); in rge_phy_config_mac_cfg2_8126()
1800 rge_write_phy_ocp(sc, 0xb87c, 0x8036); in rge_phy_config_mac_cfg2_8126()
1801 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1802 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); in rge_phy_config_mac_cfg2_8126()
1803 rge_write_phy_ocp(sc, 0xb87c, 0x8078); in rge_phy_config_mac_cfg2_8126()
1804 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1805 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); in rge_phy_config_mac_cfg2_8126()
1806 rge_write_phy_ocp(sc, 0xb87c, 0x8031); in rge_phy_config_mac_cfg2_8126()
1807 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1808 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); in rge_phy_config_mac_cfg2_8126()
1809 rge_write_phy_ocp(sc, 0xb87c, 0x8073); in rge_phy_config_mac_cfg2_8126()
1810 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1811 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); in rge_phy_config_mac_cfg2_8126()
1812 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00; in rge_phy_config_mac_cfg2_8126()
1813 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00); in rge_phy_config_mac_cfg2_8126()
1814 rge_write_phy_ocp(sc, 0xb87c, 0x89D1); in rge_phy_config_mac_cfg2_8126()
1815 rge_write_phy_ocp(sc, 0xb87e, 0x0004); in rge_phy_config_mac_cfg2_8126()
1816 rge_write_phy_ocp(sc, 0xa436, 0x8fbd); in rge_phy_config_mac_cfg2_8126()
1817 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1818 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); in rge_phy_config_mac_cfg2_8126()
1819 rge_write_phy_ocp(sc, 0xa436, 0x8fbe); in rge_phy_config_mac_cfg2_8126()
1820 rge_write_phy_ocp(sc, 0xa438, 0x0d09); in rge_phy_config_mac_cfg2_8126()
1821 rge_write_phy_ocp(sc, 0xb87c, 0x89cd); in rge_phy_config_mac_cfg2_8126()
1822 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); in rge_phy_config_mac_cfg2_8126()
1823 rge_write_phy_ocp(sc, 0xb87c, 0x89cf); in rge_phy_config_mac_cfg2_8126()
1824 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); in rge_phy_config_mac_cfg2_8126()
1825 rge_write_phy_ocp(sc, 0xb87c, 0x83a4); in rge_phy_config_mac_cfg2_8126()
1826 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_cfg2_8126()
1827 rge_write_phy_ocp(sc, 0xb87c, 0x83a6); in rge_phy_config_mac_cfg2_8126()
1828 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_cfg2_8126()
1829 rge_write_phy_ocp(sc, 0xb87c, 0x83c0); in rge_phy_config_mac_cfg2_8126()
1830 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_cfg2_8126()
1831 rge_write_phy_ocp(sc, 0xb87c, 0x83c2); in rge_phy_config_mac_cfg2_8126()
1832 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_cfg2_8126()
1833 rge_write_phy_ocp(sc, 0xb87c, 0x8414); in rge_phy_config_mac_cfg2_8126()
1834 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_cfg2_8126()
1835 rge_write_phy_ocp(sc, 0xb87c, 0x8416); in rge_phy_config_mac_cfg2_8126()
1836 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_cfg2_8126()
1837 rge_write_phy_ocp(sc, 0xb87c, 0x83f8); in rge_phy_config_mac_cfg2_8126()
1838 rge_write_phy_ocp(sc, 0xb87e, 0x6600); in rge_phy_config_mac_cfg2_8126()
1839 rge_write_phy_ocp(sc, 0xb87c, 0x83fa); in rge_phy_config_mac_cfg2_8126()
1840 rge_write_phy_ocp(sc, 0xb87e, 0x6601); in rge_phy_config_mac_cfg2_8126()
1842 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mac_cfg2_8126()
1843 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00; in rge_phy_config_mac_cfg2_8126()
1844 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000); in rge_phy_config_mac_cfg2_8126()
1845 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007; in rge_phy_config_mac_cfg2_8126()
1846 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007); in rge_phy_config_mac_cfg2_8126()
1847 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000); in rge_phy_config_mac_cfg2_8126()
1848 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380; in rge_phy_config_mac_cfg2_8126()
1849 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280); in rge_phy_config_mac_cfg2_8126()
1850 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080; in rge_phy_config_mac_cfg2_8126()
1851 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060); in rge_phy_config_mac_cfg2_8126()
1852 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010; in rge_phy_config_mac_cfg2_8126()
1853 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c); in rge_phy_config_mac_cfg2_8126()
1854 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mac_cfg2_8126()
1856 rge_write_phy_ocp(sc, 0xa436, 0x843b); in rge_phy_config_mac_cfg2_8126()
1857 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1858 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); in rge_phy_config_mac_cfg2_8126()
1859 rge_write_phy_ocp(sc, 0xa436, 0x843d); in rge_phy_config_mac_cfg2_8126()
1860 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1861 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); in rge_phy_config_mac_cfg2_8126()
1862 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f); in rge_phy_config_mac_cfg2_8126()
1863 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030); in rge_phy_config_mac_cfg2_8126()
1865 rge_write_phy_ocp(sc, 0xa436, 0x8188); in rge_phy_config_mac_cfg2_8126()
1867 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); in rge_phy_config_mac_cfg2_8126()
1869 rge_write_phy_ocp(sc, 0xb87c, 0x8015); in rge_phy_config_mac_cfg2_8126()
1870 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1871 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_cfg2_8126()
1872 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd); in rge_phy_config_mac_cfg2_8126()
1873 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1874 rge_write_phy_ocp(sc, 0xb87e, val | 0); in rge_phy_config_mac_cfg2_8126()
1875 rge_write_phy_ocp(sc, 0xb87c, 0x8fff); in rge_phy_config_mac_cfg2_8126()
1876 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1877 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00); in rge_phy_config_mac_cfg2_8126()
1878 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb); in rge_phy_config_mac_cfg2_8126()
1879 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1880 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1881 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); in rge_phy_config_mac_cfg2_8126()
1882 rge_write_phy_ocp(sc, 0xb87e, 0x0002); in rge_phy_config_mac_cfg2_8126()
1883 rge_write_phy_ocp(sc, 0xb87c, 0x8fef); in rge_phy_config_mac_cfg2_8126()
1884 rge_write_phy_ocp(sc, 0xb87e, 0x00a5); in rge_phy_config_mac_cfg2_8126()
1885 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1); in rge_phy_config_mac_cfg2_8126()
1886 rge_write_phy_ocp(sc, 0xb87e, 0x0106); in rge_phy_config_mac_cfg2_8126()
1887 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1); in rge_phy_config_mac_cfg2_8126()
1888 rge_write_phy_ocp(sc, 0xb87e, 0x0102); in rge_phy_config_mac_cfg2_8126()
1889 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3); in rge_phy_config_mac_cfg2_8126()
1890 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1891 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); in rge_phy_config_mac_cfg2_8126()
1892 RGE_PHY_SETBIT(sc, 0xa654, 0x0800); in rge_phy_config_mac_cfg2_8126()
1893 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003); in rge_phy_config_mac_cfg2_8126()
1894 rge_write_phy_ocp(sc, 0xac3a, 0x5851); in rge_phy_config_mac_cfg2_8126()
1895 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000; in rge_phy_config_mac_cfg2_8126()
1896 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000); in rge_phy_config_mac_cfg2_8126()
1897 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200; in rge_phy_config_mac_cfg2_8126()
1898 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0); in rge_phy_config_mac_cfg2_8126()
1899 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000); in rge_phy_config_mac_cfg2_8126()
1900 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038); in rge_phy_config_mac_cfg2_8126()
1901 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002; in rge_phy_config_mac_cfg2_8126()
1902 rge_write_phy_ocp(sc, 0xac42, val | 0x0005); in rge_phy_config_mac_cfg2_8126()
1903 rge_write_phy_ocp(sc, 0xac1a, 0x00db); in rge_phy_config_mac_cfg2_8126()
1904 rge_write_phy_ocp(sc, 0xade4, 0x01b5); in rge_phy_config_mac_cfg2_8126()
1905 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00); in rge_phy_config_mac_cfg2_8126()
1906 rge_write_phy_ocp(sc, 0xb87c, 0x814b); in rge_phy_config_mac_cfg2_8126()
1907 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1908 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_cfg2_8126()
1909 rge_write_phy_ocp(sc, 0xb87c, 0x814d); in rge_phy_config_mac_cfg2_8126()
1910 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1911 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); in rge_phy_config_mac_cfg2_8126()
1912 rge_write_phy_ocp(sc, 0xb87c, 0x814f); in rge_phy_config_mac_cfg2_8126()
1913 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1914 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00); in rge_phy_config_mac_cfg2_8126()
1915 rge_write_phy_ocp(sc, 0xb87c, 0x8142); in rge_phy_config_mac_cfg2_8126()
1916 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1917 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1918 rge_write_phy_ocp(sc, 0xb87c, 0x8144); in rge_phy_config_mac_cfg2_8126()
1919 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1920 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1921 rge_write_phy_ocp(sc, 0xb87c, 0x8150); in rge_phy_config_mac_cfg2_8126()
1922 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1923 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1924 rge_write_phy_ocp(sc, 0xb87c, 0x8118); in rge_phy_config_mac_cfg2_8126()
1925 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1926 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_cfg2_8126()
1927 rge_write_phy_ocp(sc, 0xb87c, 0x811a); in rge_phy_config_mac_cfg2_8126()
1928 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1929 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_cfg2_8126()
1930 rge_write_phy_ocp(sc, 0xb87c, 0x811c); in rge_phy_config_mac_cfg2_8126()
1931 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1932 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); in rge_phy_config_mac_cfg2_8126()
1933 rge_write_phy_ocp(sc, 0xb87c, 0x810f); in rge_phy_config_mac_cfg2_8126()
1934 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1935 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1936 rge_write_phy_ocp(sc, 0xb87c, 0x8111); in rge_phy_config_mac_cfg2_8126()
1937 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1938 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1939 rge_write_phy_ocp(sc, 0xb87c, 0x811d); in rge_phy_config_mac_cfg2_8126()
1940 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1941 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); in rge_phy_config_mac_cfg2_8126()
1942 RGE_PHY_SETBIT(sc, 0xac36, 0x1000); in rge_phy_config_mac_cfg2_8126()
1943 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100); in rge_phy_config_mac_cfg2_8126()
1944 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0; in rge_phy_config_mac_cfg2_8126()
1945 rge_write_phy_ocp(sc, 0xade8, val | 0x1400); in rge_phy_config_mac_cfg2_8126()
1946 rge_write_phy_ocp(sc, 0xb87c, 0x864b); in rge_phy_config_mac_cfg2_8126()
1947 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1948 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00); in rge_phy_config_mac_cfg2_8126()
1950 rge_write_phy_ocp(sc, 0xa436, 0x8f97); in rge_phy_config_mac_cfg2_8126()
1952 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); in rge_phy_config_mac_cfg2_8126()
1954 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020); in rge_phy_config_mac_cfg2_8126()
1955 rge_write_phy_ocp(sc, 0xb87c, 0x8122); in rge_phy_config_mac_cfg2_8126()
1956 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1957 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); in rge_phy_config_mac_cfg2_8126()
1959 rge_write_phy_ocp(sc, 0xb87c, 0x82c8); in rge_phy_config_mac_cfg2_8126()
1961 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); in rge_phy_config_mac_cfg2_8126()
1963 rge_write_phy_ocp(sc, 0xb87c, 0x80ef); in rge_phy_config_mac_cfg2_8126()
1964 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1965 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); in rge_phy_config_mac_cfg2_8126()
1967 rge_write_phy_ocp(sc, 0xb87c, 0x82a0); in rge_phy_config_mac_cfg2_8126()
1969 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); in rge_phy_config_mac_cfg2_8126()
1971 rge_write_phy_ocp(sc, 0xa436, 0x8018); in rge_phy_config_mac_cfg2_8126()
1972 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); in rge_phy_config_mac_cfg2_8126()
1973 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); in rge_phy_config_mac_cfg2_8126()
1974 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg2_8126()
1975 rge_write_phy_ocp(sc, 0xb87e, val | 0); in rge_phy_config_mac_cfg2_8126()
1976 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0; in rge_phy_config_mac_cfg2_8126()
1977 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700); in rge_phy_config_mac_cfg2_8126()
1981 rge_phy_config_mac_cfg3(struct rge_softc *sc) in rge_phy_config_mac_cfg3() argument
1997 rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER); in rge_phy_config_mac_cfg3()
1999 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); in rge_phy_config_mac_cfg3()
2000 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; in rge_phy_config_mac_cfg3()
2001 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); in rge_phy_config_mac_cfg3()
2002 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; in rge_phy_config_mac_cfg3()
2003 rge_write_phy_ocp(sc, 0xad32, val | 0x0006); in rge_phy_config_mac_cfg3()
2004 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); in rge_phy_config_mac_cfg3()
2005 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); in rge_phy_config_mac_cfg3()
2006 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; in rge_phy_config_mac_cfg3()
2007 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); in rge_phy_config_mac_cfg3()
2008 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; in rge_phy_config_mac_cfg3()
2009 rge_write_phy_ocp(sc, 0xad40, val | 0x0040); in rge_phy_config_mac_cfg3()
2010 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; in rge_phy_config_mac_cfg3()
2011 rge_write_phy_ocp(sc, 0xad40, val | 0x0004); in rge_phy_config_mac_cfg3()
2012 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); in rge_phy_config_mac_cfg3()
2013 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); in rge_phy_config_mac_cfg3()
2014 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; in rge_phy_config_mac_cfg3()
2015 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); in rge_phy_config_mac_cfg3()
2016 rge_write_phy_ocp(sc, 0xad4c, 0x00a8); in rge_phy_config_mac_cfg3()
2017 rge_write_phy_ocp(sc, 0xac5c, 0x01ff); in rge_phy_config_mac_cfg3()
2018 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; in rge_phy_config_mac_cfg3()
2019 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); in rge_phy_config_mac_cfg3()
2020 rge_write_phy_ocp(sc, 0xb87c, 0x8157); in rge_phy_config_mac_cfg3()
2021 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg3()
2022 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); in rge_phy_config_mac_cfg3()
2023 rge_write_phy_ocp(sc, 0xb87c, 0x8159); in rge_phy_config_mac_cfg3()
2024 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg3()
2025 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); in rge_phy_config_mac_cfg3()
2026 rge_write_phy_ocp(sc, 0xb87c, 0x80a2); in rge_phy_config_mac_cfg3()
2027 rge_write_phy_ocp(sc, 0xb87e, 0x0153); in rge_phy_config_mac_cfg3()
2028 rge_write_phy_ocp(sc, 0xb87c, 0x809c); in rge_phy_config_mac_cfg3()
2029 rge_write_phy_ocp(sc, 0xb87e, 0x0153); in rge_phy_config_mac_cfg3()
2031 rge_write_phy_ocp(sc, 0xa436, 0x81b3); in rge_phy_config_mac_cfg3()
2033 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); in rge_phy_config_mac_cfg3()
2035 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mac_cfg3()
2036 rge_write_phy_ocp(sc, 0xa436, 0x8257); in rge_phy_config_mac_cfg3()
2037 rge_write_phy_ocp(sc, 0xa438, 0x020f); in rge_phy_config_mac_cfg3()
2038 rge_write_phy_ocp(sc, 0xa436, 0x80ea); in rge_phy_config_mac_cfg3()
2039 rge_write_phy_ocp(sc, 0xa438, 0x7843); in rge_phy_config_mac_cfg3()
2041 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mac_cfg3()
2042 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); in rge_phy_config_mac_cfg3()
2043 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); in rge_phy_config_mac_cfg3()
2045 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); in rge_phy_config_mac_cfg3()
2046 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); in rge_phy_config_mac_cfg3()
2048 RGE_PHY_SETBIT(sc, 0xb896, 0x0001); in rge_phy_config_mac_cfg3()
2049 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mac_cfg3()
2051 RGE_PHY_SETBIT(sc, 0xd068, 0x2000); in rge_phy_config_mac_cfg3()
2052 rge_write_phy_ocp(sc, 0xa436, 0x81a2); in rge_phy_config_mac_cfg3()
2053 RGE_PHY_SETBIT(sc, 0xa438, 0x0100); in rge_phy_config_mac_cfg3()
2054 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; in rge_phy_config_mac_cfg3()
2055 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); in rge_phy_config_mac_cfg3()
2056 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); in rge_phy_config_mac_cfg3()
2057 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); in rge_phy_config_mac_cfg3()
2058 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); in rge_phy_config_mac_cfg3()
2059 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); in rge_phy_config_mac_cfg3()
2060 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_cfg3()
2061 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); in rge_phy_config_mac_cfg3()
2065 rge_phy_config_mac_cfg5(struct rge_softc *sc) in rge_phy_config_mac_cfg5() argument
2070 rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER); in rge_phy_config_mac_cfg5()
2072 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); in rge_phy_config_mac_cfg5()
2073 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; in rge_phy_config_mac_cfg5()
2074 rge_write_phy_ocp(sc, 0xac46, val | 0x0090); in rge_phy_config_mac_cfg5()
2075 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; in rge_phy_config_mac_cfg5()
2076 rge_write_phy_ocp(sc, 0xad30, val | 0x0001); in rge_phy_config_mac_cfg5()
2077 rge_write_phy_ocp(sc, 0xb87c, 0x80f5); in rge_phy_config_mac_cfg5()
2078 rge_write_phy_ocp(sc, 0xb87e, 0x760e); in rge_phy_config_mac_cfg5()
2079 rge_write_phy_ocp(sc, 0xb87c, 0x8107); in rge_phy_config_mac_cfg5()
2080 rge_write_phy_ocp(sc, 0xb87e, 0x360e); in rge_phy_config_mac_cfg5()
2081 rge_write_phy_ocp(sc, 0xb87c, 0x8551); in rge_phy_config_mac_cfg5()
2082 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; in rge_phy_config_mac_cfg5()
2083 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); in rge_phy_config_mac_cfg5()
2084 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; in rge_phy_config_mac_cfg5()
2085 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); in rge_phy_config_mac_cfg5()
2086 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; in rge_phy_config_mac_cfg5()
2087 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); in rge_phy_config_mac_cfg5()
2089 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); in rge_phy_config_mac_cfg5()
2090 rge_write_phy_ocp(sc, 0xa438, 0x2417); in rge_phy_config_mac_cfg5()
2092 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); in rge_phy_config_mac_cfg5()
2093 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; in rge_phy_config_mac_cfg5()
2094 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); in rge_phy_config_mac_cfg5()
2095 rge_write_phy_ocp(sc, 0xa436, 0x8170); in rge_phy_config_mac_cfg5()
2096 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; in rge_phy_config_mac_cfg5()
2097 rge_write_phy_ocp(sc, 0xa438, val | 0xd800); in rge_phy_config_mac_cfg5()
2098 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); in rge_phy_config_mac_cfg5()
2102 rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version) in rge_phy_config_mcu() argument
2104 if (sc->rge_mcodever != mcode_version) { in rge_phy_config_mcu()
2107 rge_patch_phy_mcu(sc, 1); in rge_phy_config_mcu()
2109 if (sc->rge_type == MAC_CFG3) { in rge_phy_config_mcu()
2110 rge_write_phy_ocp(sc, 0xa436, 0x8024); in rge_phy_config_mcu()
2111 rge_write_phy_ocp(sc, 0xa438, 0x8601); in rge_phy_config_mcu()
2112 rge_write_phy_ocp(sc, 0xa436, 0xb82e); in rge_phy_config_mcu()
2113 rge_write_phy_ocp(sc, 0xa438, 0x0001); in rge_phy_config_mcu()
2115 RGE_PHY_SETBIT(sc, 0xb820, 0x0080); in rge_phy_config_mcu()
2118 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
2123 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); in rge_phy_config_mcu()
2125 rge_write_phy_ocp(sc, 0xa436, 0); in rge_phy_config_mcu()
2126 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mcu()
2127 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); in rge_phy_config_mcu()
2128 rge_write_phy_ocp(sc, 0xa436, 0x8024); in rge_phy_config_mcu()
2129 rge_write_phy_ocp(sc, 0xa438, 0); in rge_phy_config_mcu()
2130 } else if (sc->rge_type == MAC_CFG5) { in rge_phy_config_mcu()
2132 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
2136 } else if (sc->rge_type == MAC_CFG2_8126) { in rge_phy_config_mcu()
2138 rge_write_phy_ocp(sc, in rge_phy_config_mcu()
2144 rge_patch_phy_mcu(sc, 0); in rge_phy_config_mcu()
2147 rge_write_phy_ocp(sc, 0xa436, 0x801e); in rge_phy_config_mcu()
2148 rge_write_phy_ocp(sc, 0xa438, mcode_version); in rge_phy_config_mcu()
2153 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) in rge_set_macaddr() argument
2155 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_set_macaddr()
2156 RGE_WRITE_4(sc, RGE_MAC0, in rge_set_macaddr()
2158 RGE_WRITE_4(sc, RGE_MAC4, in rge_set_macaddr()
2160 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_set_macaddr()
2164 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) in rge_get_macaddr() argument
2169 addr[i] = RGE_READ_1(sc, RGE_MAC0 + i); in rge_get_macaddr()
2171 *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0); in rge_get_macaddr()
2172 *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1); in rge_get_macaddr()
2174 rge_set_macaddr(sc, addr); in rge_get_macaddr()
2178 rge_hw_init(struct rge_softc *sc) in rge_hw_init() argument
2183 rge_disable_aspm_clkreq(sc); in rge_hw_init()
2184 RGE_CLRBIT_1(sc, 0xf1, 0x80); in rge_hw_init()
2187 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); in rge_hw_init()
2190 rge_disable_aspm_clkreq(sc); in rge_hw_init()
2191 rge_write_mac_ocp(sc, 0xfc48, 0); in rge_hw_init()
2193 rge_write_mac_ocp(sc, reg, 0); in rge_hw_init()
2195 rge_write_mac_ocp(sc, 0xfc26, 0); in rge_hw_init()
2197 if (sc->rge_type == MAC_CFG3) { in rge_hw_init()
2199 rge_switch_mcu_ram_page(sc, npages); in rge_hw_init()
2202 rge_write_mac_ocp(sc, in rge_hw_init()
2206 rge_write_mac_ocp(sc, in rge_hw_init()
2210 rge_write_mac_ocp(sc, in rge_hw_init()
2215 rge_write_mac_ocp(sc, 0xf9f8, 0x6486); in rge_hw_init()
2216 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15); in rge_hw_init()
2217 rge_write_mac_ocp(sc, 0xf9fc, 0x090e); in rge_hw_init()
2218 rge_write_mac_ocp(sc, 0xf9fe, 0x1139); in rge_hw_init()
2221 rge_write_mac_ocp(sc, 0xfc26, 0x8000); in rge_hw_init()
2222 rge_write_mac_ocp(sc, 0xfc2a, 0x0540); in rge_hw_init()
2223 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06); in rge_hw_init()
2224 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8); in rge_hw_init()
2225 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c); in rge_hw_init()
2226 rge_write_mac_ocp(sc, 0xfc34, 0x10a8); in rge_hw_init()
2227 rge_write_mac_ocp(sc, 0xfc40, 0x0d54); in rge_hw_init()
2228 rge_write_mac_ocp(sc, 0xfc42, 0x0e24); in rge_hw_init()
2229 rge_write_mac_ocp(sc, 0xfc48, 0x307a); in rge_hw_init()
2230 } else if (sc->rge_type == MAC_CFG5) { in rge_hw_init()
2231 rge_switch_mcu_ram_page(sc, 0); in rge_hw_init()
2233 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, in rge_hw_init()
2239 if (sc->rge_type == MAC_CFG3) in rge_hw_init()
2240 rge_disable_phy_ocp_pwrsave(sc); in rge_hw_init()
2243 rge_write_csi(sc, 0x108, in rge_hw_init()
2244 rge_read_csi(sc, 0x108) | 0x00100000); in rge_hw_init()
2248 rge_hw_reset(struct rge_softc *sc) in rge_hw_reset() argument
2251 RGE_WRITE_4(sc, RGE_IMR, 0); in rge_hw_reset()
2252 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); in rge_hw_reset()
2255 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); in rge_hw_reset()
2256 RGE_WRITE_4(sc, RGE_TIMERINT1, 0); in rge_hw_reset()
2257 RGE_WRITE_4(sc, RGE_TIMERINT2, 0); in rge_hw_reset()
2258 RGE_WRITE_4(sc, RGE_TIMERINT3, 0); in rge_hw_reset()
2260 rge_reset(sc); in rge_hw_reset()
2264 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) in rge_disable_phy_ocp_pwrsave() argument
2266 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { in rge_disable_phy_ocp_pwrsave()
2267 rge_patch_phy_mcu(sc, 1); in rge_disable_phy_ocp_pwrsave()
2268 rge_write_phy_ocp(sc, 0xc416, 0); in rge_disable_phy_ocp_pwrsave()
2269 rge_write_phy_ocp(sc, 0xc416, 0x0500); in rge_disable_phy_ocp_pwrsave()
2270 rge_patch_phy_mcu(sc, 0); in rge_disable_phy_ocp_pwrsave()
2275 rge_patch_phy_mcu(struct rge_softc *sc, int set) in rge_patch_phy_mcu() argument
2280 RGE_PHY_SETBIT(sc, 0xb820, 0x0010); in rge_patch_phy_mcu()
2282 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); in rge_patch_phy_mcu()
2286 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0) in rge_patch_phy_mcu()
2289 if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040)) in rge_patch_phy_mcu()
2296 sc->sc_dev.dv_xname); in rge_patch_phy_mcu()
2300 rge_add_media_types(struct rge_softc *sc) in rge_add_media_types() argument
2302 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); in rge_add_media_types()
2303 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); in rge_add_media_types()
2304 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); in rge_add_media_types()
2305 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); in rge_add_media_types()
2306 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL); in rge_add_media_types()
2307 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); in rge_add_media_types()
2308 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL); in rge_add_media_types()
2309 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); in rge_add_media_types()
2311 if (sc->rge_type == MAC_CFG2_8126) { in rge_add_media_types()
2312 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL); in rge_add_media_types()
2313 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX, in rge_add_media_types()
2319 rge_config_imtype(struct rge_softc *sc, int imtype) in rge_config_imtype() argument
2323 sc->rge_intrs = RGE_INTRS; in rge_config_imtype()
2326 sc->rge_intrs = RGE_INTRS_TIMER; in rge_config_imtype()
2329 panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); in rge_config_imtype()
2334 rge_disable_aspm_clkreq(struct rge_softc *sc) in rge_disable_aspm_clkreq() argument
2336 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_disable_aspm_clkreq()
2337 if (sc->rge_type == MAC_CFG2_8126) in rge_disable_aspm_clkreq()
2338 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08); in rge_disable_aspm_clkreq()
2340 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); in rge_disable_aspm_clkreq()
2341 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); in rge_disable_aspm_clkreq()
2342 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_disable_aspm_clkreq()
2346 rge_disable_hw_im(struct rge_softc *sc) in rge_disable_hw_im() argument
2348 RGE_WRITE_2(sc, RGE_IM, 0); in rge_disable_hw_im()
2352 rge_disable_sim_im(struct rge_softc *sc) in rge_disable_sim_im() argument
2354 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); in rge_disable_sim_im()
2355 sc->rge_timerintr = 0; in rge_disable_sim_im()
2359 rge_setup_sim_im(struct rge_softc *sc) in rge_setup_sim_im() argument
2361 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); in rge_setup_sim_im()
2362 RGE_WRITE_4(sc, RGE_TIMERCNT, 1); in rge_setup_sim_im()
2363 sc->rge_timerintr = 1; in rge_setup_sim_im()
2367 rge_setup_intr(struct rge_softc *sc, int imtype) in rge_setup_intr() argument
2369 rge_config_imtype(sc, imtype); in rge_setup_intr()
2372 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); in rge_setup_intr()
2376 rge_disable_sim_im(sc); in rge_setup_intr()
2377 rge_disable_hw_im(sc); in rge_setup_intr()
2380 rge_disable_hw_im(sc); in rge_setup_intr()
2381 rge_setup_sim_im(sc); in rge_setup_intr()
2384 panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype); in rge_setup_intr()
2389 rge_switch_mcu_ram_page(struct rge_softc *sc, int page) in rge_switch_mcu_ram_page() argument
2393 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003; in rge_switch_mcu_ram_page()
2395 rge_write_mac_ocp(sc, 0xe446, val); in rge_switch_mcu_ram_page()
2399 rge_exit_oob(struct rge_softc *sc) in rge_exit_oob() argument
2403 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | in rge_exit_oob()
2408 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); in rge_exit_oob()
2410 rge_reset(sc); in rge_exit_oob()
2413 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); in rge_exit_oob()
2415 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); in rge_exit_oob()
2419 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) in rge_exit_oob()
2423 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); in rge_exit_oob()
2424 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); in rge_exit_oob()
2425 rge_write_mac_ocp(sc, 0xc01e, 0x5555); in rge_exit_oob()
2429 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) in rge_exit_oob()
2433 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { in rge_exit_oob()
2435 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) in rge_exit_oob()
2439 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100); in rge_exit_oob()
2440 if (sc->rge_type != MAC_CFG3) in rge_exit_oob()
2441 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); in rge_exit_oob()
2442 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); in rge_exit_oob()
2447 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) in rge_write_csi() argument
2451 RGE_WRITE_4(sc, RGE_CSIDR, val); in rge_write_csi()
2452 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | in rge_write_csi()
2457 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)) in rge_write_csi()
2465 rge_read_csi(struct rge_softc *sc, uint32_t reg) in rge_read_csi() argument
2469 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | in rge_read_csi()
2474 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY) in rge_read_csi()
2480 return (RGE_READ_4(sc, RGE_CSIDR)); in rge_read_csi()
2484 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_mac_ocp() argument
2491 RGE_WRITE_4(sc, RGE_MACOCP, tmp); in rge_write_mac_ocp()
2495 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) in rge_read_mac_ocp() argument
2500 RGE_WRITE_4(sc, RGE_MACOCP, val); in rge_read_mac_ocp()
2502 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK); in rge_read_mac_ocp()
2506 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_ephy() argument
2513 RGE_WRITE_4(sc, RGE_EPHYAR, tmp); in rge_write_ephy()
2517 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY)) in rge_write_ephy()
2525 rge_read_ephy(struct rge_softc *sc, uint16_t reg) in rge_read_ephy() argument
2531 RGE_WRITE_4(sc, RGE_EPHYAR, val); in rge_read_ephy()
2535 val = RGE_READ_4(sc, RGE_EPHYAR); in rge_read_ephy()
2546 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) in rge_write_phy() argument
2557 rge_write_phy_ocp(sc, phyaddr, val); in rge_write_phy()
2561 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) in rge_read_phy() argument
2572 return (rge_read_phy_ocp(sc, phyaddr)); in rge_read_phy()
2576 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) in rge_write_phy_ocp() argument
2583 RGE_WRITE_4(sc, RGE_PHYOCP, tmp); in rge_write_phy_ocp()
2587 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY)) in rge_write_phy_ocp()
2593 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) in rge_read_phy_ocp() argument
2599 RGE_WRITE_4(sc, RGE_PHYOCP, val); in rge_read_phy_ocp()
2603 val = RGE_READ_4(sc, RGE_PHYOCP); in rge_read_phy_ocp()
2612 rge_get_link_status(struct rge_softc *sc) in rge_get_link_status() argument
2614 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0); in rge_get_link_status()
2620 struct rge_softc *sc = arg; in rge_txstart() local
2622 RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START); in rge_txstart()
2628 struct rge_softc *sc = arg; in rge_tick() local
2632 rge_link_state(sc); in rge_tick()
2635 timeout_add_sec(&sc->sc_timeout, 1); in rge_tick()
2639 rge_link_state(struct rge_softc *sc) in rge_link_state() argument
2641 struct ifnet *ifp = &sc->sc_arpcom.ac_if; in rge_link_state()
2644 if (rge_get_link_status(sc)) in rge_link_state()
2657 struct rge_softc *sc = ifp->if_softc; in rge_wol() local
2660 if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) { in rge_wol()
2662 "cannot do WOL\n", sc->sc_dev.dv_xname); in rge_wol()
2668 rge_iff(sc); in rge_wol()
2671 RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001); in rge_wol()
2673 RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001); in rge_wol()
2675 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_wol()
2676 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST | in rge_wol()
2678 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC); in rge_wol()
2680 RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE); in rge_wol()
2681 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); in rge_wol()
2687 rge_wol_power(struct rge_softc *sc) in rge_wol_power() argument
2690 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); in rge_wol_power()
2693 RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN); in rge_wol_power()
2694 RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN); in rge_wol_power()
2762 struct rge_softc *sc = ks->ks_softc; in rge_kstat_read() local
2770 command = RGE_READ_1(sc, RGE_CMD); in rge_kstat_read()
2777 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, in rge_kstat_read()
2780 RGE_WRITE_4(sc, RGE_DTCCR_HI, cmd >> 32); in rge_kstat_read()
2781 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_HI, 8, in rge_kstat_read()
2783 RGE_WRITE_4(sc, RGE_DTCCR_LO, cmd); in rge_kstat_read()
2784 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_LO, 4, in rge_kstat_read()
2789 reg = RGE_READ_4(sc, RGE_DTCCR_LO); in rge_kstat_read()
2794 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, in rge_kstat_read()
2798 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, in rge_kstat_read()
2835 rge_kstat_attach(struct rge_softc *sc) in rge_kstat_attach() argument
2843 sc->sc_dev.dv_xname); in rge_kstat_attach()
2847 if (bus_dmamap_create(sc->sc_dmat, in rge_kstat_attach()
2852 sc->sc_dev.dv_xname); in rge_kstat_attach()
2856 if (bus_dmamem_alloc(sc->sc_dmat, in rge_kstat_attach()
2861 sc->sc_dev.dv_xname); in rge_kstat_attach()
2865 if (bus_dmamem_map(sc->sc_dmat, in rge_kstat_attach()
2870 sc->sc_dev.dv_xname); in rge_kstat_attach()
2874 if (bus_dmamap_load(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map, in rge_kstat_attach()
2878 sc->sc_dev.dv_xname); in rge_kstat_attach()
2882 ks = kstat_create(sc->sc_dev.dv_xname, 0, "re-stats", 0, in rge_kstat_attach()
2886 sc->sc_dev.dv_xname); in rge_kstat_attach()
2894 ks->ks_softc = sc; in rge_kstat_attach()
2901 sc->sc_kstat = ks; in rge_kstat_attach()
2906 bus_dmamap_unload(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map); in rge_kstat_attach()
2908 bus_dmamem_unmap(sc->sc_dmat, in rge_kstat_attach()
2911 bus_dmamem_free(sc->sc_dmat, &rge_ks_sc->rge_ks_sc_seg, 1); in rge_kstat_attach()
2913 bus_dmamap_destroy(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map); in rge_kstat_attach()