2097 	DNPRINTF(QWZ_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);  in qwz_mhi_register()
2104 	DNPRINTF(QWZ_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);  in qwz_mhi_unregister()
2620 	DNPRINTF(QWZ_D_MHI, "%s: start MHI channel %d in state %d\n", __func__,  in qwz_mhi_start_channel()
2727 	DNPRINTF(QWZ_D_MHI, "%s: BHI offset 0x%x\n", __func__, psc->bhi_off);  in qwz_mhi_start()
2730 	DNPRINTF(QWZ_D_MHI, "%s: BHIE offset 0x%x\n", __func__, psc->bhie_off);  in qwz_mhi_start()
2759 	DNPRINTF(QWZ_D_MHI, "%s: MHI power on with EE: 0x%x, status: 0x%x\n",  in qwz_mhi_start()
2766 		DNPRINTF(QWZ_D_MHI, "%s: MHI state after reset: 0x%x\n",  in qwz_mhi_start()
2822 	DNPRINTF(QWZ_D_MHI, "%s: MHISTATUS 0x%x\n", sc->sc_dev.dv_xname, reg);  in qwz_mhi_reset_device()
2957 		DNPRINTF(QWZ_D_MHI, "%s: MHI_CTRL is 0x%x\n", __func__, reg);  in qwz_mhi_await_device_reset()
2964 		DNPRINTF(QWZ_D_MHI, "%s: MHI reset failed\n", __func__);  in qwz_mhi_await_device_reset()
2983 		DNPRINTF(QWZ_D_MHI, "%s: MHI_STATUS is 0x%x\n", __func__, reg);  in qwz_mhi_await_device_ready()
3175 		DNPRINTF(QWZ_D_MHI, "%s: BHI status is 0x%x EE is 0x%x\n",  in qwz_mhi_fw_load_bhi()
3271 		DNPRINTF(QWZ_D_MHI, "%s: txvec state is 0x%x\n", __func__,  in qwz_mhi_fw_load_bhie()
3477 			DNPRINTF(QWZ_D_MHI, "%s: new EE PBL\n",  in qwz_mhi_state_change()
3483 			DNPRINTF(QWZ_D_MHI, "%s: new EE SBL\n",  in qwz_mhi_state_change()
3487 			DNPRINTF(QWZ_D_MHI, "%s: new EE AMSS\n",  in qwz_mhi_state_change()
3494 			DNPRINTF(QWZ_D_MHI, "%s: new EE WFW\n",  in qwz_mhi_state_change()
3510 			DNPRINTF(QWZ_D_MHI, "%s: new MHI state RESET\n",  in qwz_mhi_state_change()
3515 			DNPRINTF(QWZ_D_MHI, "%s: new MHI state READY\n",  in qwz_mhi_state_change()
3521 			DNPRINTF(QWZ_D_MHI, "%s: new MHI state M0\n",  in qwz_mhi_state_change()
3527 			DNPRINTF(QWZ_D_MHI, "%s: new MHI state M1\n",  in qwz_mhi_state_change()
3533 			DNPRINTF(QWZ_D_MHI,  in qwz_mhi_state_change()
3554 	DNPRINTF(QWZ_D_MHI, "%s: MHI state change 0x%x -> 0x%x\n", __func__,  in qwz_pci_intr_ctrl_event_mhi()
3564 	DNPRINTF(QWZ_D_MHI, "%s: EE change 0x%x to 0x%x\n", __func__,  in qwz_pci_intr_ctrl_event_ee()
3634 	DNPRINTF(QWZ_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);  in qwz_pci_intr_ctrl_event()
3635 	DNPRINTF(QWZ_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);  in qwz_pci_intr_ctrl_event()
3636 	DNPRINTF(QWZ_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);  in qwz_pci_intr_ctrl_event()
3637 	DNPRINTF(QWZ_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);  in qwz_pci_intr_ctrl_event()
3660 		DNPRINTF(QWZ_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",  in qwz_pci_intr_ctrl_event()
3745 			DNPRINTF(QWZ_D_MHI, "%s:%d: ring->rp 0x%llx "  in qwz_pci_intr_data_event_tx()
3761 			DNPRINTF(QWZ_D_MHI, "%s: chan %u data (len %u): ",  in qwz_pci_intr_data_event_tx()
3765 				DNPRINTF(QWZ_D_MHI, "%02x ",  in qwz_pci_intr_data_event_tx()
3769 				DNPRINTF(QWZ_D_MHI, "...");  in qwz_pci_intr_data_event_tx()
3770 			DNPRINTF(QWZ_D_MHI, "\n");  in qwz_pci_intr_data_event_tx()
3857 	DNPRINTF(QWZ_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);  in qwz_pci_intr_data_event()
3858 	DNPRINTF(QWZ_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);  in qwz_pci_intr_data_event()
3859 	DNPRINTF(QWZ_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);  in qwz_pci_intr_data_event()
3860 	DNPRINTF(QWZ_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);  in qwz_pci_intr_data_event()
3881 		DNPRINTF(QWZ_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",  in qwz_pci_intr_data_event()
3956 	DNPRINTF(QWZ_D_MHI,  in qwz_pci_intr()