Lines Matching refs:vddc
1709 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_and_t_formula() local
1714 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_and_t_formula()
1723 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; in si_calculate_leakage_for_v_and_t_formula()
1726 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); in si_calculate_leakage_for_v_and_t_formula()
1728 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_and_t_formula()
1747 s64 kt, kv, leakage_w, i_leakage, vddc; in si_calculate_leakage_for_v_formula() local
1750 vddc = div64_s64(drm_int2fixp(v), 1000); in si_calculate_leakage_for_v_formula()
1754 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1756 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); in si_calculate_leakage_for_v_formula()
2229 SISLANDS_SMC_VOLTAGE_VALUE vddc; in si_populate_power_containment_values() local
2286 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2290 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2295 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2299 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2485 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2486 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2487 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2488 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2910 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules() local
2968 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
2969 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
2977 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
2978 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3027 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3030 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3043 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3054 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3060 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3061 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3089 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3090 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3093 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3099 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3102 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3107 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3108 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3114 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3172 u16 vddc, count = 0; in si_get_leakage_vddc() local
3176 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3178 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3179 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
4102 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4105 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4117 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4120 …>pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; in si_get_std_voltage_value()
4127 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4356 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4357 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4363 &table->initialState.level.vddc, in si_populate_smc_initial_state()
4367 table->initialState.level.vddc.index, in si_populate_smc_initial_state()
4380 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4383 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4450 pi->acpi_vddc, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4455 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4458 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4469 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4473 pi->min_vddc_in_table, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4478 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4482 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4496 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4587 state->level.std_vddc = state->level.vddc; in si_populate_ulv_state()
4696 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
4984 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
4989 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
4994 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
5008 pl->vddc, in si_convert_power_level_to_smc()
5011 &level->vddc); in si_convert_power_level_to_smc()
5100 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5236 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5609 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
6687 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6696 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6699 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6702 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6718 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6719 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6721 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6722 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6726 u16 vddc, vddci, mvdd; in si_parse_pplib_clock_info() local
6727 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6730 pl->vddc = vddc; in si_parse_pplib_clock_info()
6739 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7045 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()