Lines Matching refs:write32
1036 sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val); in qwx_hw_ipq8074_reo_setup()
1038 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_0(sc), in qwx_hw_ipq8074_reo_setup()
1040 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_1(sc), in qwx_hw_ipq8074_reo_setup()
1042 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_2(sc), in qwx_hw_ipq8074_reo_setup()
1044 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_3(sc), in qwx_hw_ipq8074_reo_setup()
1047 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, in qwx_hw_ipq8074_reo_setup()
1049 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, in qwx_hw_ipq8074_reo_setup()
1051 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in qwx_hw_ipq8074_reo_setup()
1053 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, in qwx_hw_ipq8074_reo_setup()
1135 sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val); in qwx_hw_wcn6855_reo_setup()
1141 sc->ops.write32(sc, reo_base + HAL_REO1_MISC_CTL(sc), val); in qwx_hw_wcn6855_reo_setup()
1143 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_0(sc), in qwx_hw_wcn6855_reo_setup()
1145 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_1(sc), in qwx_hw_wcn6855_reo_setup()
1147 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_2(sc), in qwx_hw_wcn6855_reo_setup()
1149 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_3(sc), in qwx_hw_wcn6855_reo_setup()
1152 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in qwx_hw_wcn6855_reo_setup()
1154 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, in qwx_hw_wcn6855_reo_setup()
1181 sc->ops.write32(sc, reo_base + HAL_REO1_GEN_ENABLE, val); in qwx_hw_ipq5018_reo_setup()
1183 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_0(sc), in qwx_hw_ipq5018_reo_setup()
1185 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_1(sc), in qwx_hw_ipq5018_reo_setup()
1187 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_2(sc), in qwx_hw_ipq5018_reo_setup()
1189 sc->ops.write32(sc, reo_base + HAL_REO1_AGING_THRESH_IX_3(sc), in qwx_hw_ipq5018_reo_setup()
1192 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, in qwx_hw_ipq5018_reo_setup()
1194 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, in qwx_hw_ipq5018_reo_setup()
1196 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in qwx_hw_ipq5018_reo_setup()
1198 sc->ops.write32(sc, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, in qwx_hw_ipq5018_reo_setup()
9354 sc->ops.write32(sc, in qwx_hal_srng_access_end()
9359 sc->ops.write32(sc, in qwx_hal_srng_access_end()
9478 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9482 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9486 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9490 sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_WBM_REG + in qwx_hal_setup_link_idle_list()
9498 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9502 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9508 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9513 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9516 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9521 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9526 sc->ops.write32(sc, in qwx_hal_setup_link_idle_list()
9960 sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG + in qwx_hal_tx_set_dscp_tid_map()
9991 sc->ops.write32(sc, addr, *(uint32_t *)&hw_map_val[i]); in qwx_hal_tx_set_dscp_tid_map()
9999 sc->ops.write32(sc, HAL_SEQ_WCSS_UMAC_TCL_REG + in qwx_hal_tx_set_dscp_tid_map()
20510 sc->ops.write32(sc, in qwx_hal_srng_dst_hw_init()
20517 sc->ops.write32(sc, in qwx_hal_srng_dst_hw_init()
20520 sc->ops.write32(sc, in qwx_hal_srng_dst_hw_init()
20525 sc->ops.write32(sc, reg_base, srng->ring_base_paddr); in qwx_hal_srng_dst_hw_init()
20531 sc->ops.write32(sc, in qwx_hal_srng_dst_hw_init()
20536 sc->ops.write32(sc, reg_base + HAL_REO1_RING_ID_OFFSET(sc), val); in qwx_hal_srng_dst_hw_init()
20545 sc->ops.write32(sc, in qwx_hal_srng_dst_hw_init()
20550 sc->ops.write32(sc, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc), in qwx_hal_srng_dst_hw_init()
20552 sc->ops.write32(sc, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc), in qwx_hal_srng_dst_hw_init()
20557 sc->ops.write32(sc, reg_base, 0); in qwx_hal_srng_dst_hw_init()
20558 sc->ops.write32(sc, reg_base + HAL_REO1_RING_TP_OFFSET(sc), 0); in qwx_hal_srng_dst_hw_init()
20571 sc->ops.write32(sc, reg_base + HAL_REO1_RING_MISC_OFFSET(sc), val); in qwx_hal_srng_dst_hw_init()
20585 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20592 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20596 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20601 sc->ops.write32(sc, reg_base, srng->ring_base_paddr); in qwx_hal_srng_src_hw_init()
20607 sc->ops.write32(sc, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(sc), val); in qwx_hal_srng_src_hw_init()
20610 sc->ops.write32(sc, reg_base + HAL_TCL1_RING_ID_OFFSET(sc), val); in qwx_hal_srng_src_hw_init()
20613 sc->ops.write32(sc, reg_base, (uint32_t)srng->ring_base_paddr); in qwx_hal_srng_src_hw_init()
20619 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20633 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20641 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20648 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20651 sc->ops.write32(sc, in qwx_hal_srng_src_hw_init()
20658 sc->ops.write32(sc, reg_base, 0); in qwx_hal_srng_src_hw_init()
20659 sc->ops.write32(sc, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); in qwx_hal_srng_src_hw_init()
20676 sc->ops.write32(sc, reg_base + HAL_TCL1_RING_MISC_OFFSET(sc), val); in qwx_hal_srng_src_hw_init()
20703 sc->ops.write32(sc, addr, val); in qwx_hal_ce_dst_setup()