Lines Matching refs:devhandle

91 int64_t	hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino,
107 int64_t	hv_vintr_getcookie(uint64_t devhandle, uint64_t devino,
109 int64_t	hv_vintr_setcookie(uint64_t devhandle, uint64_t devino,
111 int64_t	hv_vintr_getenabled(uint64_t devhandle, uint64_t devino,
113 int64_t	hv_vintr_setenabled(uint64_t devhandle, uint64_t devino,
115 int64_t	hv_vintr_getstate(uint64_t devhandle, uint64_t devino,
117 int64_t	hv_vintr_setstate(uint64_t devhandle, uint64_t devino,
119 int64_t	hv_vintr_gettarget(uint64_t devhandle, uint64_t devino,
121 int64_t	hv_vintr_settarget(uint64_t devhandle, uint64_t devino,
156 int64_t	hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid,
159 int64_t	hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid,
161 int64_t	hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid,
163 int64_t	hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr,
166 int64_t	hv_pci_config_get(uint64_t devhandle, uint64_t pci_device,
169 int64_t	hv_pci_config_put(uint64_t devhandle, uint64_t pci_device,
180 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid,
182 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid,
185 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid,
187 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid,
193 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid,
195 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid,
201 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid,
203 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid,
205 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid,
208 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum,
210 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum,
216 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum,
218 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum,
221 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum,
223 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum,
229 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg,
231 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg,
234 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg,
236 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg,
292 int64_t hv_pci_iov_root_configured(uint64_t devhandle);
293 int64_t	hv_pci_real_config_get(uint64_t devhandle, uint64_t pci_device,
296 int64_t	hv_pci_real_config_put(uint64_t devhandle, uint64_t pci_device,
299 int64_t hv_pci_error_send(uint64_t devhandle, uint64_t devino,