Lines Matching refs:Target

31 MipsGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
33 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
36 MipsGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
38 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
41 MipsGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
43 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
46 MipsGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
48 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
51 MipsGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
53 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
56 MipsGenFastISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
58 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
61 MipsGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
63 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
66 MipsGenPostLegalizeGICombiner.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
69 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
72 MipsGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
74 MipsGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
76 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
79 MipsGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
81 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
84 MipsGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
86 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
89 MipsGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
91 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
94 MipsGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
96 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
99 MipsGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
101 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
104 MipsGenExegesis.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
106 		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \