Lines Matching refs:Target
30 ARMGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
32 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
35 ARMGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
37 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
40 ARMGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
42 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
45 ARMGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
47 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
50 ARMGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
52 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
55 ARMGenFastISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
57 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
60 ARMGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
62 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
65 ARMGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
67 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
70 ARMGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
72 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
75 ARMGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
77 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
80 ARMGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
82 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
85 ARMGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
87 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
90 ARMGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
92 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
95 ARMGenSystemRegister.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
97 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \