Lines Matching refs:mips_builtin_opcodes
189 * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and
209 (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
546 (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
571 (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro
644 * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s
1306 * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO,
1310 (mips_builtin_opcodes): Remove all uses of M1.
1312 * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2
1324 * mips-opc.c (mips_builtin_opcodes): Finish additions
1339 mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
1354 (mips_builtin_opcodes) Replace all uses of P4 with I32.
1454 * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores.