53                                       unsigned &RegToUseForCFI) const {  in regNeedsCFI()
71 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()  argument
125 AArch64RegisterInfo::getDarwinCalleeSavedRegs(const MachineFunction *MF) const {  in getDarwinCalleeSavedRegs()  argument
169     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()  argument
178     MachineFunction &MF) const {  in UpdateCustomCalleeSavedRegs()
196                                        unsigned Idx) const {  in getSubClassWithSubReg()
209                                                 CallingConv::ID CC) const {  in getDarwinCallPreservedMask()
245                                           CallingConv::ID CC) const {  in getCallPreservedMask()
289     const MachineFunction &MF) const {  in getCustomEHPadPreservedMask()  argument
305                                                  const uint32_t **Mask) const {  in UpdateCustomCallPreservedMask()  argument
339                                                 CallingConv::ID CC) const {  in getThisReturnPreservedMask()
359                                         MCRegister PhysReg) const {  in explainReservedReg()
385 AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {  in getStrictlyReservedRegs()  argument
434 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()  argument
447                                         MCRegister Reg) const {  in isReservedReg()
452                                                 MCRegister Reg) const {  in isStrictlyReservedReg()
456 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {  in isAnyArgRegReserved()  argument
463     const MachineFunction &MF) const {  in emitReservedArgRegCallError()  argument
470                                           MCRegister PhysReg) const {  in isAsmClobberable()
483                                       unsigned Kind) const {  in getPointerRegClass()
488 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {  in getCrossCopyRegClass()  argument
496 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()  argument
533                                              MCRegister Reg) const {  in isArgumentRegister()
596 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()  argument
602     const MachineFunction &MF) const {  in requiresRegisterScavenging()  argument
607     const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()  argument
612 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {  in useFPForScavengingIndex()  argument
630     const MachineFunction &MF) const {  in requiresFrameIndexScavenging()  argument
635 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()  argument
647                                             int64_t Offset) const {  in needsFrameBaseReg()
712                                              int64_t Offset) const {  in isFrameOffsetLegal()
723                                                   int64_t Offset) const {  in materializeFrameBaseRegister()
746                                             int64_t Offset) const {  in resolveFrameIndex()
794     const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {  in getOffsetOpcodes()
822                                               RegScavenger *RS) const {  in eliminateFrameIndex()
914                                                   MachineFunction &MF) const {  in getRegPressureLimit()
959   const MachineFunction &MF) const {  in getLocalAddressRegister()  argument
972     const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {  in shouldCoalesce()