Lines Matching refs:DD_CSR
285 nd_bsw4(DD_CSR, DMACSR_RESET | DMACSR_CLRCOMPLETE); in nextdma_init()
286 nd_bsw4(DD_CSR, 0); in nextdma_init()
296 state = nd_bsr4 (DD_CSR); in nextdma_init()
331 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in nextdma_reset()
584 state = nd_bsr4(DD_CSR); in nextdma_enet_intr()
745 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | dmadir); in nextdma_enet_intr()
748 nd_bsw4(DD_CSR, in nextdma_enet_intr()
754 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); in nextdma_enet_intr()
876 nd_bsw4(DD_CSR, (turbo ? in nextdma_start()
878 nd_bsw4(DD_CSR, 0); in nextdma_start()
889 nd_bsw4(DD_CSR, DMACSR_SETENABLE | dmadir); in nextdma_start()
891 nd_bsw4(DD_CSR, DMACSR_SETSUPDATE | DMACSR_SETENABLE | dmadir); in nextdma_start()
916 dd_csr = nd_bsr4(DD_CSR); in nextdma_print()