183 #define CACHE_TAG(cache, set, way) ( \  argument
184   & ((cache)->tag_storage[(set) * (cache)->ways + (way)]) \
188 #define CACHE_ADDRESS_TAG(cache, address) ( \  argument
189   (address) & ~(((cache)->line_size * (cache)->sets) - 1) \
193 #define CACHE_TAG_SET_START(cache, tag) ( \  argument
194   ((tag) - (cache)->tag_storage) & ~((cache)->ways - 1) \
198 #define CACHE_TAG_SET_NUMBER(cache, tag) ( \  argument
199   CACHE_TAG_SET_START ((cache), (tag)) / (cache)->ways \
202 #define CACHE_RETURN_DATA(cache, slot, address, mode, N) (               \  argument
203   T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
204                          [((address) & ((cache)->line_size - 1))]))          \
206 #define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) (              \  argument
207   ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address)  \
208                                                      & ((cache)->line_size - 1)]) \
211 #define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \  argument
212   ((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
215 #define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)  argument