Lines Matching refs:gencode
152 @SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
167 @SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
214 @SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
316 @SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
940 @SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_2 = cr16/gencode$(EXEEXT)
941 @SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 = d10v/gencode$(EXEEXT)
943 @SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 = m68hc11/gencode$(EXEEXT)
949 @SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_8 = sh/gencode$(EXEEXT)
1019 @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode.$(OBJEXT)
1037 @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode.$(OBJEXT)
1117 @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode.$(OBJEXT)
1195 @SIM_ENABLE_ARCH_sh_TRUE@am_sh_gencode_OBJECTS = sh/gencode.$(OBJEXT)
2250 @SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode$(EXEEXT) \
2253 @SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
2326 @SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode$(EXEEXT) \
2329 @SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
2662 @SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode$(EXEEXT) \
2666 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
3177 @SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \
3182 @SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
3904 cr16/gencode.$(OBJEXT): cr16/$(am__dirstamp) \
3907 @SIM_ENABLE_ARCH_cr16_FALSE@cr16/gencode$(EXEEXT): $(cr16_gencode_OBJECTS) $(cr16_gencode_DEPENDENC…
3908 @SIM_ENABLE_ARCH_cr16_FALSE@ @rm -f cr16/gencode$(EXEEXT)
3924 d10v/gencode.$(OBJEXT): d10v/$(am__dirstamp) \
3927 @SIM_ENABLE_ARCH_d10v_FALSE@d10v/gencode$(EXEEXT): $(d10v_gencode_OBJECTS) $(d10v_gencode_DEPENDENC…
3928 @SIM_ENABLE_ARCH_d10v_FALSE@ @rm -f d10v/gencode$(EXEEXT)
4008 m68hc11/gencode.$(OBJEXT): m68hc11/$(am__dirstamp) \
4011 @SIM_ENABLE_ARCH_m68hc11_FALSE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_genco…
4012 @SIM_ENABLE_ARCH_m68hc11_FALSE@ @rm -f m68hc11/gencode$(EXEEXT)
4084 sh/gencode.$(OBJEXT): sh/$(am__dirstamp) sh/$(DEPDIR)/$(am__dirstamp)
4086 @SIM_ENABLE_ARCH_sh_FALSE@sh/gencode$(EXEEXT): $(sh_gencode_OBJECTS) $(sh_gencode_DEPENDENCIES) $(E…
4087 @SIM_ENABLE_ARCH_sh_FALSE@ @rm -f sh/gencode$(EXEEXT)
4176 @AMDEP_TRUE@@am__include@ @am__quote@cr16/$(DEPDIR)/gencode.Po@am__quote@
4180 @AMDEP_TRUE@@am__include@ @am__quote@d10v/$(DEPDIR)/gencode.Po@am__quote@
4210 @AMDEP_TRUE@@am__include@ @am__quote@m68hc11/$(DEPDIR)/gencode.Po@am__quote@
4238 @AMDEP_TRUE@@am__include@ @am__quote@sh/$(DEPDIR)/gencode.Po@am__quote@
5221 @SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode$(EXEEXT): $(cr16_gencode_OBJECTS) $(cr16_gencode_DEPENDENCI…
5225 @SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode.o: cr16/gencode.c
5230 @SIM_ENABLE_ARCH_cr16_TRUE@cr16/simops.h: cr16/gencode$(EXEEXT)
5233 @SIM_ENABLE_ARCH_cr16_TRUE@cr16/table.c: cr16/gencode$(EXEEXT)
5287 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode$(EXEEXT): $(d10v_gencode_OBJECTS) $(d10v_gencode_DEPENDENCI…
5291 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode.o: d10v/gencode.c
5296 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/simops.h: d10v/gencode$(EXEEXT)
5299 @SIM_ENABLE_ARCH_d10v_TRUE@d10v/table.c: d10v/gencode$(EXEEXT)
5502 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_gencod…
5506 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode.o: m68hc11/gencode.c
5509 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc11int.c: m68hc11/gencode$(EXEEXT)
5512 @SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT)
5953 @SIM_ENABLE_ARCH_sh_TRUE@sh/gencode$(EXEEXT): $(sh_gencode_OBJECTS) $(sh_gencode_DEPENDENCIES) sh/$…
5957 @SIM_ENABLE_ARCH_sh_TRUE@sh/gencode.o: sh/gencode.c
5960 @SIM_ENABLE_ARCH_sh_TRUE@sh/code.c: sh/gencode$(EXEEXT)
5963 @SIM_ENABLE_ARCH_sh_TRUE@sh/ppi.c: sh/gencode$(EXEEXT)
5966 @SIM_ENABLE_ARCH_sh_TRUE@sh/table.c: sh/gencode$(EXEEXT)