Lines Matching refs:Rt
10140 unsigned Rt = inst.operands[0].reg; in do_vmrs() local
10142 if (thumb_mode && Rt == REG_SP) in do_vmrs()
10186 if (!inst.operands[0].isvec && Rt == REG_PC) in do_vmrs()
10195 inst.instruction |= (Rt << 12); in do_vmrs()
10201 unsigned Rt = inst.operands[1].reg; in do_vmsr() local
10204 reject_bad_reg (Rt); in do_vmsr()
10205 else if (Rt == REG_PC) in do_vmsr()
10251 inst.instruction |= (Rt << 12); in do_vmsr()
20075 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; in do_mve_mov() local
20080 Rt = 2; in do_mve_mov()
20087 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg, in do_mve_mov()
20089 constraint (inst.operands[Rt].reg == REG_SP in do_mve_mov()
20092 constraint (inst.operands[Rt].reg == REG_PC in do_mve_mov()
20102 inst.instruction |= inst.operands[Rt].reg; in do_mve_mov()