Lines Matching refs:EN_WRITE

331 #define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))  macro
351 	EN_WRITE((SC), (SC)->dtq_us, \
355 	EN_WRITE((SC), (SC)->drq_us, \
361 	EN_WRITE((SC), (SC)->dtq_us, \
365 	EN_WRITE((SC), (SC)->drq_us, \
372 	  EN_WRITE((SC), (SC)->dtq_us, \
375 	  EN_WRITE((SC), (SC)->dtq_us, \
381 	  EN_WRITE((SC), (SC)->drq_us, \
384 	  EN_WRITE((SC), (SC)->drq_us, \
396 	EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
400 	  EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
409 	EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
413 	  EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
685   EN_WRITE(sc, MID_RESID, 0x0);	/* reset card before touching RAM */
687     EN_WRITE(sc, lcv, lcv);	/* data[address] = address */
711   EN_WRITE(sc, MID_RESID, 0x0);		/* reset */
713     EN_WRITE(sc, lcv, 0);	/* zero memory */
960   EN_WRITE(sc, MID_RESID, 0x0);	/* reset card before touching RAM */
963   EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
964   EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT) 
966   EN_WRITE(sc, MID_DST_RP(0), 0);
967   EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
971   EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA);	/* enable DMA (only) */
993       EN_WRITE(sc, MID_BUFOFF+cnt, 0);	/* zero memory */
1006       EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
1008       EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
1009     EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1010     EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1027     EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA);   /* re-enable DMA (only) */
1032       EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1034       EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1035     EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1036     EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1053     EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA);   /* re-enable DMA (only) */
1249   EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1298   EN_WRITE(sc, MID_RESID, 0x0);	/* reset hardware */
1383   EN_WRITE(sc, MID_RESID, 0x0);		/* reset */
1405   EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip)); 
1412   EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip)); 
1427     EN_WRITE(sc, MIDX_READPTR(slot), 0);
1428     EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1433     EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1444   EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1447   EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1467   EN_WRITE(sc, MID_VC(vc), reg);
1474   EN_WRITE(sc, MID_DST_RP(vc), 0);	/* read pointer = 0, desc. start = 0 */
1475   EN_WRITE(sc, MID_WP_ST_CNT(vc), 0);	/* write pointer = 0 */
1476   EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode);  /* set mode, size, loc */
2047     EN_WRITE(sc, cur, l->tbd1);
2049     EN_WRITE(sc, cur, l->tbd2);
2314       EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2557 	EN_WRITE(sc, MID_VC(vci), MIDV_TRASH);  /* rx off, damn it! */
2560       EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */