Lines Matching refs:samp

52 @cindex @samp{--32} option, i386
53 @cindex @samp{--32} option, x86-64
54 @cindex @samp{--64} option, i386
55 @cindex @samp{--64} option, x86-64
93 require a @samp{%} prefix.  AT&T System V/386 assembler syntax is quite
115 AT&T immediate operands are preceded by @samp{$}; Intel immediate
116 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
117 AT&T register operands are preceded by @samp{%}; Intel register operands
119 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
127 operands.  Intel @samp{add eax, 4} is @samp{addl $4, %eax}.  The
128 @samp{source, dest} convention is maintained for compatibility with
130 source operand, such as the @samp{enter} instruction, do @emph{not} have
141 character of the instruction mnemonic.  Mnemonic suffixes of @samp{b},
142 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
145 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}.  Thus,
146 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
155 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
157 @samp{call/jmp far @var{section}:@var{offset}}.  Also, the far return
159 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
160 @samp{ret far @var{stack-adjust}}.
180 specify the size of operands.  The letters @samp{b}, @samp{w}, @samp{l}
181 and @samp{q} specify byte, word, long and quadruple word operands.  If
184 (the last one by convention).  Thus, @samp{mov %ax, %bx} is equivalent
185 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
186 @samp{movw $1, bx}.  Note that this is incompatible with the AT&T Unix
197 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
198 and @samp{movzx} in Intel syntax).  The instruction mnemonic suffixes
200 @emph{to} suffix.  Thus, @samp{movsbl %al, %edx} is AT&T syntax for
202 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
203 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
204 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
215 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
218 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
221 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
224 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
227 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
231 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
232 @samp{%rdx:%rax} (x86-64 only),
236 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
237 @samp{cqto} in AT&T naming.  @code{@value{AS}} accepts either naming for these
244 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
245 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
255 Register operands are always prefixed with @samp{%}.  The 80386 registers
260 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
261 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
262 frame pointer), and @samp{%esp} (the stack pointer).
265 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
266 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
269 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
270 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
271 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
272 @samp{%cx}, and @samp{%dx})
275 the 6 section registers @samp{%cs} (code section), @samp{%ds}
276 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
277 and @samp{%gs}.
280 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
281 @samp{%cr3}.
284 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
285 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
288 the 2 test registers @samp{%tr6} and @samp{%tr7}.
291 the 8 floating point register stack @samp{%st} or equivalently
292 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
293 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
294 These registers are overloaded by 8 MMX registers @samp{%mm0},
295 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
296 @samp{%mm6} and @samp{%mm7}.
299 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
300 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
307 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
308 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
309 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
313 the 8 extended registers @samp{%r8}--@samp{%r15}.
316 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
319 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
322 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
325 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
328 the 8 debug registers: @samp{%db8}--@samp{%db15}.
331 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
346 they act upon. For example, the @samp{scas} (scan string) instruction is
362 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
363 @samp{fs}, @samp{gs}.  These are automatically added by specifying
368 Operand/Address size prefixes @samp{data16} and @samp{addr16}
370 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
383 The bus lock prefix @samp{lock} inhibits interrupts during execution of
389 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
395 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
396 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
400 The @samp{rex} family of prefixes is used by x86-64 to encode
401 extensions to i386 instruction set.  The @samp{rex} prefix has four
406 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
407 instruction emits @samp{rex} prefix with all the bits set.  By omitting
443 be preceded by a @samp{%}.  If you specify a section override which
452 @item AT&T: @samp{-4(%ebp)}, Intel:  @samp{[ebp - 4]}
453 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
454 missing, and the default section is used (@samp{%ss} for addressing with
455 @samp{%ebp} as the base register).  @var{index}, @var{scale} are both missing.
457 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
458 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
459 @samp{foo}.  All other fields are missing.  The section register here
460 defaults to @samp{%ds}.
462 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
463 This uses the value pointed to by @samp{foo} as a memory operand.
465 @emph{one} @samp{,}.  This is a syntactic exception.
467 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
468 This selects the contents of the variable @samp{foo} with section
469 register @var{section} being @samp{%gs}.
473 prefixed with @samp{*}.  If no @samp{*} is specified, @code{@value{AS}}
478 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
482 addressing.  This addressing mode is specified by using @samp{rip} as a
486 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
490 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
510 instruction with the @samp{data16} instruction prefix), since the 80386
511 insists upon masking @samp{%eip} to 16 bits after the word displacement
514 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
515 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
518 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
553 Floating point constructors are @samp{.float} or @samp{.single},
554 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
555 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
556 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real.  The 80387
557 only supports this format via the @samp{fldt} (load 80-bit real to stack
558 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
569 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
570 @samp{.quad} for the 16-, 32-, and 64-bit integer formats.  The
571 corresponding instruction mnemonic suffixes are @samp{s} (single),
572 @samp{l} (long), and @samp{q} (quad).  As with the 80-bit real format,
573 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
574 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
579 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
580 wrote @samp{fst %st, %st(1)}, since all register to register operations
581 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
582 which converts @samp{%st} from 80-bit to 64-bit floating point format,
583 then stores the result in the 4 byte location @samp{mem})
605 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
606 @samp{%mm1}, ... @samp{%mm7}.  They contain eight 8-bit integers, four
628 mode code segments.  To do this, put a @samp{.code16} or
629 @samp{.code16gcc} directive before the assembly language instructions to
631 normal 32-bit code with the @samp{.code32} directive.
633 @samp{.code16gcc} provides experimental support for generating 16-bit
634 code from gcc, and differs from @samp{.code16} in that @samp{call},
635 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
636 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
640 @samp{.code16gcc} also automatically adds address size prefixes where
653 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
654 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
661 opcode bytes @samp{6a 04} (ie. without the operand size prefix), which
680 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
681 than the expected @samp{%st(3) - %st}.  This happens with all the
683 operands where the source register is @samp{%st} and the destination
684 register is @samp{%st(i)}.
700 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
701 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
702 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
703 @item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
704 @item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
709 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
713 explicitly request the two byte opcode by writing @samp{sarl %eax}.
714 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
715 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
721 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
722 control automatic promotion of conditional jumps. @samp{jumps} is the
725 (@pxref{i386-Jumps})  @samp{nojumps} leaves external conditional jumps as
728 Unconditional jumps are treated as for @samp{jumps}.
744 There is some trickery concerning the @samp{mul} and @samp{imul}
746 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
747 for @samp{imul}) can be output only in the one operand form.  Thus,
748 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
749 the expanding multiply would clobber the @samp{%edx} register, and this
750 would confuse @code{@value{GCC}} output.  Use @samp{imul %ebx} to get the
751 64-bit product in @samp{%edx:%eax}.
753 We have added a two operand form of @samp{imul} when the first operand
755 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
756 example, can be done with @samp{imul $69, %eax} rather than @samp{imul