365 	link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);  in axge_miibus_statchg()
398 	axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);  in axge_miibus_statchg()
399 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);  in axge_miibus_statchg()
409 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);  in axge_chip_init()
410 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);  in axge_chip_init()
412 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,  in axge_chip_init()
464 	axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,  in axge_attach_post()
623 		val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR);  in axge_detach()
625 		axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val);  in axge_detach()
627 		axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0);  in axge_detach()
629 		axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0);  in axge_detach()
813 		axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);  in axge_rxfilter()
820 	axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);  in axge_rxfilter()
821 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);  in axge_rxfilter()
858 	axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,  in axge_init()
861 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);  in axge_init()
862 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);  in axge_init()
877 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0);  in axge_init()
878 	(void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR);  in axge_init()
881 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD |  in axge_init()
903 	val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR);  in axge_stop()
905 	axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);  in axge_stop()
1094 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);  in axge_csum_cfg()
1099 	axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);  in axge_csum_cfg()