Lines Matching full:pad

1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
26 pad controller and the XUSB controller as "ports". This is confusing since
64 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
70 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
72 Pad nodes:
76 of the pads exposed by the XUSB pad controller. Each pad may need additional
77 resources that can be referenced in its pad node.
79 The "status" property is used to enable or disable the use of a pad. If set
80 to "disabled", the pad will not be used on the given board. In order to use
81 the pad and any of its lanes, this property must be set to "okay".
87 a description of the properties of each pad.
89 UTMI pad:
97 HSIC pad:
105 PCIe pad:
116 SATA pad:
128 Each pad node has a child named "lanes" that contains one or more children of
129 its own, each representing one of the lanes controlled by the pad.
173 by the XUSB pad controller. Per-port configuration is only required for USB.
246 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
253 For Tegra210, the XUSB pad controller exposes the following ports:
258 For Tegra194, the XUSB pad controller exposes the following ports: