Lines Matching full:pll

53   silabs,pll-source:
56       A list of cell pairs containing a PLL index and its source. Allows to
60         - description: PLL A (0) or PLL B (1)
62         - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
65   silabs,pll-reset-mode:
69     description: A list of cell pairs containing a PLL index and its reset mode.
72         - description: PLL A (0) or PLL B (1)
75             Reset mode for the PLL. Mode can be one of:
77                 0 - reset whenever PLL rate is adjusted (default mode)
78                 1 - do not reset when PLL rate is adjusted
80             In mode 1, the PLL is only reset if the silabs,pll-reset is
82             the PLL. This mode may be preferable if output clocks are expected
118           Source PLL A (0) or B (1) for the corresponding multisynth divider.
120       silabs,pll-master:
123           The frequency of the source PLL is allowed to be changed by the
126       silabs,pll-reset:
128         description: Reset the source PLL when enabling this clock output.
217         silabs,pll-source = <0 0>, <1 0>;
220         silabs,pll-reset-mode = <1 1>;
235           silabs,pll-master;
252           silabs,pll-master;
253           silabs,pll-reset;