Lines Matching refs:uint64_t
51 uint64_t elr_el1; /* Exception Link Register */
52 uint64_t sp_el0; /* Stack pointer */
53 uint64_t tpidr_el0; /* EL0 Software ID Register */
54 uint64_t tpidrro_el0; /* Read-only Thread ID Register */
55 uint64_t tpidr_el1; /* EL1 Software ID Register */
56 uint64_t vbar_el1; /* Vector Base Address Register */
58 uint64_t actlr_el1; /* Auxiliary Control Register */
59 uint64_t afsr0_el1; /* Auxiliary Fault Status Register 0 */
60 uint64_t afsr1_el1; /* Auxiliary Fault Status Register 1 */
61 uint64_t amair_el1; /* Auxiliary Memory Attribute Indirection Register */
62 uint64_t contextidr_el1; /* Current Process Identifier */
63 uint64_t cpacr_el1; /* Architectural Feature Access Control Register */
64 uint64_t csselr_el1; /* Cache Size Selection Register */
65 uint64_t esr_el1; /* Exception Syndrome Register */
66 uint64_t far_el1; /* Fault Address Register */
67 uint64_t mair_el1; /* Memory Attribute Indirection Register */
68 uint64_t mdccint_el1; /* Monitor DCC Interrupt Enable Register */
69 uint64_t mdscr_el1; /* Monitor Debug System Control Register */
70 uint64_t par_el1; /* Physical Address Register */
71 uint64_t sctlr_el1; /* System Control Register */
72 uint64_t tcr_el1; /* Translation Control Register */
73 uint64_t tcr2_el1; /* Translation Control Register 2 */
74 uint64_t ttbr0_el1; /* Translation Table Base Register 0 */
75 uint64_t ttbr1_el1; /* Translation Table Base Register 1 */
76 uint64_t spsr_el1; /* Saved Program Status Register */
78 uint64_t pmcr_el0; /* Performance Monitors Control Register */
79 uint64_t pmccntr_el0;
80 uint64_t pmccfiltr_el0;
81 uint64_t pmcntenset_el0;
82 uint64_t pmintenset_el1;
83 uint64_t pmovsset_el0;
84 uint64_t pmselr_el0;
85 uint64_t pmuserenr_el0;
86 uint64_t pmevcntr_el0[31];
87 uint64_t pmevtyper_el0[31];
89 uint64_t dbgbcr_el1[16]; /* Debug Breakpoint Control Registers */
90 uint64_t dbgbvr_el1[16]; /* Debug Breakpoint Value Registers */
91 uint64_t dbgwcr_el1[16]; /* Debug Watchpoint Control Registers */
92 uint64_t dbgwvr_el1[16]; /* Debug Watchpoint Value Registers */
95 uint64_t cptr_el2; /* Architectural Feature Trap Register */
96 uint64_t hcr_el2; /* Hypervisor Configuration Register */
97 uint64_t hcrx_el2; /* Extended Hypervisor Configuration Register */
98 uint64_t mdcr_el2; /* Monitor Debug Configuration Register */
99 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
100 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
101 uint64_t el2_addr; /* The address of this in el2 space */
105 uint64_t far_el2; /* Fault Address Register */
106 uint64_t hpfar_el2; /* Hypervisor IPA Fault Address Register */
111 uint64_t setcaps; /* Currently enabled capabilities. */
114 uint64_t debug_spsr; /* Saved guest SPSR */
115 uint64_t debug_mdscr; /* Saved guest MDSCR */
125 uint64_t vmid_generation;
126 uint64_t vttbr_el2;
127 uint64_t el2_addr; /* The address of this in el2 space */
140 uint64_t gla, int prot, uint64_t *gpa, int *is_fault))
147 DEFINE_VMMOPS_IFUNC(int, exception, (void *vcpui, uint64_t esr, uint64_t far))
148 DEFINE_VMMOPS_IFUNC(int, getreg, (void *vcpui, int num, uint64_t *retval))
149 DEFINE_VMMOPS_IFUNC(int, setreg, (void *vcpui, int num, uint64_t val))
160 DEFINE_VMMOPS_IFUNC(int, restore_tsc, (void *vcpui, uint64_t now))
164 uint64_t vmm_call_hyp(uint64_t, ...);
173 void raise_data_insn_abort(struct hypctx *, uint64_t, bool, int);