2449 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) {  in getLMUL()
2459     return RISCVII::VLMUL::LMUL_F8;  in getLMUL()
2461     return RISCVII::VLMUL::LMUL_F4;  in getLMUL()
2463     return RISCVII::VLMUL::LMUL_F2;  in getLMUL()
2465     return RISCVII::VLMUL::LMUL_1;  in getLMUL()
2467     return RISCVII::VLMUL::LMUL_2;  in getLMUL()
2469     return RISCVII::VLMUL::LMUL_4;  in getLMUL()
2471     return RISCVII::VLMUL::LMUL_8;  in getLMUL()
2475 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {  in getRegClassIDForLMUL()
2479   case RISCVII::VLMUL::LMUL_F8:  in getRegClassIDForLMUL()
2480   case RISCVII::VLMUL::LMUL_F4:  in getRegClassIDForLMUL()
2481   case RISCVII::VLMUL::LMUL_F2:  in getRegClassIDForLMUL()
2482   case RISCVII::VLMUL::LMUL_1:  in getRegClassIDForLMUL()
2484   case RISCVII::VLMUL::LMUL_2:  in getRegClassIDForLMUL()
2486   case RISCVII::VLMUL::LMUL_4:  in getRegClassIDForLMUL()
2488   case RISCVII::VLMUL::LMUL_8:  in getRegClassIDForLMUL()
2494   RISCVII::VLMUL LMUL = getLMUL(VT);  in getSubregIndexByMVT()
2495   if (LMUL == RISCVII::VLMUL::LMUL_F8 ||  in getSubregIndexByMVT()
2496       LMUL == RISCVII::VLMUL::LMUL_F4 ||  in getSubregIndexByMVT()
2497       LMUL == RISCVII::VLMUL::LMUL_F2 ||  in getSubregIndexByMVT()
2498       LMUL == RISCVII::VLMUL::LMUL_1) {  in getSubregIndexByMVT()
2503   if (LMUL == RISCVII::VLMUL::LMUL_2) {  in getSubregIndexByMVT()
2508   if (LMUL == RISCVII::VLMUL::LMUL_4) {  in getSubregIndexByMVT()
4161   case RISCVII::VLMUL::LMUL_2:  in lowerBUILD_VECTOR()
4164   case RISCVII::VLMUL::LMUL_4:  in lowerBUILD_VECTOR()
4167   case RISCVII::VLMUL::LMUL_8:  in lowerBUILD_VECTOR()
8860         RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(I32VT);  in lowerVectorIntrinsicScalars()
8875       RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(VT);  in lowerVectorIntrinsicScalars()
8972   unsigned VLMUL = (unsigned)RISCVVType::encodeLMUL(LMulVal, Fractional);  in lowerGetVectorLength()  local
8977   SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT);  in lowerGetVectorLength()
10386          getLMUL(ContainerSubVecVT) == RISCVII::VLMUL::LMUL_1);  in lowerEXTRACT_SUBVECTOR()
17929       RISCVII::VLMUL VLMUL =  in computeKnownBitsForTargetNode()  local
17930           static_cast<RISCVII::VLMUL>(Op.getConstantOperandVal(HasAVL + 2));  in computeKnownBitsForTargetNode()
17932       auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL);  in computeKnownBitsForTargetNode()
18544 lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {  in lookupMaskedIntrinsic()
18587   RISCVII::VLMUL LMul = RISCVII::getLMul(MI.getDesc().TSFlags);  in emitVFROUND_NOEXCEPT_MASK()