633 	u64 control_1;  member
900 	u64 control_1;  member
1204 	u64 control_1;  member
1446 	rxdp->control_1 &= ~VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK;  in vxge_hal_ring_rxd_1b_set()
1447 	rxdp->control_1 |= VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(size);  in vxge_hal_ring_rxd_1b_set()
1475 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK);  in vxge_hal_ring_rxd_3b_set()
1476 	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(sizes[0]);  in vxge_hal_ring_rxd_3b_set()
1478 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK);  in vxge_hal_ring_rxd_3b_set()
1479 	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(sizes[1]);  in vxge_hal_ring_rxd_3b_set()
1481 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK);  in vxge_hal_ring_rxd_3b_set()
1482 	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(sizes[2]);  in vxge_hal_ring_rxd_3b_set()
1512 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK);  in vxge_hal_ring_rxd_5b_set()
1513 	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(sizes[0]);  in vxge_hal_ring_rxd_5b_set()
1515 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK);  in vxge_hal_ring_rxd_5b_set()
1516 	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(sizes[1]);  in vxge_hal_ring_rxd_5b_set()
1518 	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK);  in vxge_hal_ring_rxd_5b_set()
1519 	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(sizes[2]);  in vxge_hal_ring_rxd_5b_set()
1690 	    (u32) VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_1b_get()
1722 	sizes[0] = (u32) VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_3b_get()
1725 	sizes[1] = (u32) VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_3b_get()
1728 	sizes[2] = (u32) VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_3b_get()
1759 	sizes[0] = (u32) VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_5b_get()
1762 	sizes[1] = (u32) VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_5b_get()
1765 	sizes[2] = (u32) VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(rxdp->control_1);  in vxge_hal_ring_rxd_5b_get()
1814 	    (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1);  in vxge_hal_ring_rxd_1b_info_get()
1824 	    (u32) VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1);  in vxge_hal_ring_rxd_1b_info_get()
1867 	    (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1);  in vxge_hal_ring_rxd_3b_5b_info_get()
2216 	u64 control_1;  member
2447 	txdp->control_1 |= cksum_bits;  in vxge_hal_fifo_txdl_cksum_set_bits()
2467 	txdp->control_1 |= interrupt_type;  in vxge_hal_fifo_txdl_interrupt_type_set()
2529 	txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_ENABLE;  in vxge_hal_fifo_txdl_vlan_set()
2530 	txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_TAG(vlan_tag);  in vxge_hal_fifo_txdl_vlan_set()