43                                            unsigned &SubIdx) const {  in isCoalescableExtInstr()
49                                              int &FrameIndex) const {  in isLoadFromStackSlot()
55                                                    int &FrameIndex) const {  in isLoadFromStackSlotPostFE()
62                                           int &FrameIndex) const {  in hasLoadFromStackSlot()
67                                               int &FrameIndex) const {  in isStoreFromStackSlot()
72                                                     int &FrameIndex) const {  in isStoreFromStackSlotPostFE()
78                                            int &FrameIndex) const {  in hasStoreFromStackSlot()
86                                       LiveVariables *LV) const {  in convertToThreeAddress()
91                                         MachineBasicBlock &MBB) const {  in getNextBranchInstr()
112                                     const TargetRegisterInfo *TRI) const {  in storeRegToStackSlot()  argument
121                                      const TargetRegisterInfo *TRI) const {  in loadRegFromStackSlot()  argument
125 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
178                                       int FrameIndex) const {  in foldMemoryOperandImpl()
186                                       MachineInstr *LoadMI) const {  in foldMemoryOperandImpl()
192                                      const SmallVectorImpl<unsigned> &Ops) const {  in canFoldMemoryOperand()  argument
200                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {  in unfoldMemoryOperand()
207                                     SmallVectorImpl<SDNode*> &NewNodes) const {  in unfoldMemoryOperand()
215                                            unsigned *LoadRegIndex) const {  in getOpcodeAfterMemoryUnfold()
222                                              unsigned NumLoads) const {  in shouldScheduleLoadsNear()
232 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)  in ReverseBranchCondition()
238                                 MachineBasicBlock::iterator MI) const {  in insertNoop()
242 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()  argument
248                                   const SmallVectorImpl<MachineOperand> &Pred2)  in SubsumesPredicate()
255                                       std::vector<MachineOperand> &Pred) const {  in DefinesPredicate()
260 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
266 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {  in isSafeToMoveRegClassDefs()  argument
271 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {  in isRegisterStore()  argument
275 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {  in isRegisterLoad()  argument
279 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {  in getIndirectIndexBegin()  argument
314 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {  in getIndirectIndexEnd()  argument
332     DebugLoc DL) const {  in convertToISA()
352 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {  in getMaskedMIMGOp()