Lines Matching defs:const

73                                              int &FrameIndex) const {  in isLoadFromStackSlot()
100 int &FrameIndex) const { in isStoreToStackSlot()
122 DebugLoc DL) const{ in InsertBranch()
176 bool AllowModify) const { in AnalyzeBranch()
307 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { in RemoveBranch()
341 int &Mask, int &Value) const { in analyzeCompare()
416 bool KillSrc) const { in copyPhysReg()
473 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot() argument
510 SmallVectorImpl<MachineInstr*> &NewMIs) const in storeRegToAddr()
520 const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot() argument
550 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
558 int FI) const { in foldMemoryOperandImpl()
563 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { in createVR()
581 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { in isExtendable() argument
606 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { in isExtended() argument
621 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const { in isBranch() argument
625 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const { in isNewValueInst() argument
635 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { in isSaveCalleeSavedRegsCall() argument
639 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable()
730 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { in getInvertedPredicatedOpcode() argument
753 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { in isNewValueStore() argument
759 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const { in isNewValueStore()
766 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { in getMatchingCondBranchOpcode()
803 const SmallVectorImpl<MachineOperand> &Cond) const { in PredicateInstruction() argument
956 const BranchProbability &Probability) const { in isProfitableToIfCvt() argument
969 const BranchProbability &Probability) const { in isProfitableToIfCvt() argument
979 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() argument
985 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated()
991 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const { in isPredicatedTrue() argument
999 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const { in isPredicatedTrue()
1008 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const { in isPredicatedNew() argument
1015 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const { in isPredicatedNew()
1023 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const { in mayBeNewStore() argument
1034 std::vector<MachineOperand> &Pred) const { in DefinesPredicate()
1052 const SmallVectorImpl<MachineOperand> &Pred2) const { in SubsumesPredicate() argument
1063 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
1075 const BranchProbability &Probability) const { in isProfitableToDupForIfCvt() argument
1079 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { in isDeallocRet() argument
1095 isValidOffset(const int Opcode, const int Offset) const { in isValidOffset() argument
1189 isValidAutoIncImm(const EVT VT, const int Offset) const { in isValidAutoIncImm() argument
1215 isMemOp(const MachineInstr *MI) const { in isMemOp() argument
1252 isSpillPredRegOp(const MachineInstr *MI) const { in isSpillPredRegOp() argument
1261 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { in isNewValueJumpCandidate() argument
1275 isConditionalTransfer (const MachineInstr *MI) const { in isConditionalTransfer() argument
1290 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { in isConditionalALU32() argument
1327 isConditionalLoad (const MachineInstr* MI) const { in isConditionalLoad() argument
1421 isConditionalStore (const MachineInstr* MI) const { in isConditionalStore() argument
1503 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { in isNewValueJump() argument
1509 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { in isPostIncrement() argument
1513 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const { in isNewValue() argument
1520 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const { in isDotNewInst() argument
1534 int HexagonInstrInfo::GetDotOldOp(const int opc) const { in GetDotOldOp() argument
1551 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const { in GetDotNewOp() argument
1581 *MBPI) const { in GetDotNewPredOp()
1616 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const { in getAddrMode() argument
1624 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const { in immediateExtend()
1639 const ScheduleDAG *DAG) const { in CreateTargetScheduleState() argument
1646 const MachineFunction &MF) const { in isSchedulingBoundary() argument
1663 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const { in isConstExtended()
1716 MachineBranchProbabilityInfo *MBPI) const { in getDotNewPredJumpOp()
1740 unsigned short OperandNum) const { in isOperandExtended()
1752 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const { in getCExtOpNum() argument
1758 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const { in getMinValue() argument
1772 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const { in getMaxValue() argument
1787 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const { in NonExtEquivalentExists() argument
1821 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const { in getNonExtOpcode() argument
1843 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const { in PredOpcodeHasJMP_c()
1852 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const { in PredOpcodeHasNot()