263       SDep Dep;  in addPhysRegDataDeps()  local
265         Dep = SDep(SU, SDep::Artificial);  in addPhysRegDataDeps()
270         Dep = SDep(SU, SDep::Data, *Alias);  in addPhysRegDataDeps()
273       Dep.setLatency(  in addPhysRegDataDeps()
277       ST.adjustSchedDependency(SU, UseSU, Dep);  in addPhysRegDataDeps()
278       UseSU->addPred(Dep);  in addPhysRegDataDeps()
311           SDep Dep(SU, Kind, /*Reg=*/*Alias);  in addPhysRegDeps()  local
312           Dep.setLatency(  in addPhysRegDeps()
314           DefSU->addPred(Dep);  in addPhysRegDeps()
388       SDep Dep(SU, SDep::Output, Reg);  in addVRegDefDeps()  local
389       Dep.setLatency(  in addVRegDefDeps()
391       DefSU->addPred(Dep);  in addVRegDefDeps()
623       SDep Dep(SU, SDep::MayAliasMem);  in adjustChainDeps()  local
624       Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);  in adjustChainDeps()
625       (*I)->addPred(Dep);  in adjustChainDeps()
648     SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);  in addChainDependency()  local
649     Dep.setLatency(TrueMemOrderLatency);  in addChainDependency()
650     SUb->addPred(Dep);  in addChainDependency()
800       SDep Dep(SU, SDep::Artificial);  in buildSchedGraph()  local
801       Dep.setLatency(SU->Latency - 1);  in buildSchedGraph()
802       ExitSU.addPred(Dep);  in buildSchedGraph()
825           SDep Dep(SU, SDep::Barrier);  in buildSchedGraph()  local
826           Dep.setLatency(TrueMemOrderLatency);  in buildSchedGraph()
827           I->second[i]->addPred(Dep);  in buildSchedGraph()