Lines Matching refs:XWRITE4
261 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); in xhci_reset_command_queue_locked()
262 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); in xhci_reset_command_queue_locked()
264 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); in xhci_reset_command_queue_locked()
265 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); in xhci_reset_command_queue_locked()
296 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); in xhci_reset_command_queue_locked()
297 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); in xhci_reset_command_queue_locked()
328 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); in xhci_start_controller()
333 XWRITE4(sc, oper, XHCI_USBSTS, temp); in xhci_start_controller()
335 XWRITE4(sc, oper, XHCI_DNCTRL, 0); in xhci_start_controller()
356 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); in xhci_start_controller()
357 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
358 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); in xhci_start_controller()
359 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
365 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); in xhci_start_controller()
368 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); in xhci_start_controller()
397 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); in xhci_start_controller()
398 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); in xhci_start_controller()
404 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); in xhci_start_controller()
405 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); in xhci_start_controller()
410 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_start_controller()
418 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); in xhci_start_controller()
419 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); in xhci_start_controller()
426 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | in xhci_start_controller()
436 XWRITE4(sc, oper, XHCI_USBCMD, 0); in xhci_start_controller()
466 XWRITE4(sc, oper, XHCI_USBCMD, 0); in xhci_halt_controller()
491 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); in xhci_reset_controller()
1110 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); in xhci_interrupt_poll()
1111 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); in xhci_interrupt_poll()
1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); in xhci_do_command()
1612 XWRITE4(sc, oper, XHCI_USBSTS, status); in xhci_interrupt()
1620 XWRITE4(sc, runt, XHCI_IMAN(0), temp); in xhci_interrupt()
2804 XWRITE4(sc, door, XHCI_DOORBELL(index), in xhci_endpoint_doorbell()
3371 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); in xhci_roothub_exec()
3374 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); in xhci_roothub_exec()
3378 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); in xhci_roothub_exec()
3381 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); in xhci_roothub_exec()
3384 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); in xhci_roothub_exec()
3387 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); in xhci_roothub_exec()
3390 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); in xhci_roothub_exec()
3394 XWRITE4(sc, oper, port, v | XHCI_PS_PED); in xhci_roothub_exec()
3397 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); in xhci_roothub_exec()
3400 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); in xhci_roothub_exec()
3406 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3414 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3560 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
3571 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
3574 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); in xhci_roothub_exec()
3577 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3593 XWRITE4(sc, oper, port, v | in xhci_roothub_exec()
3598 XWRITE4(sc, oper, port, v | XHCI_PS_PR); in xhci_roothub_exec()
3602 XWRITE4(sc, oper, port, v | XHCI_PS_PP); in xhci_roothub_exec()
3613 XWRITE4(sc, oper, port, v); in xhci_roothub_exec()
4219 XWRITE4(sc, door, XHCI_DOORBELL(index), in xhci_device_resume()