Lines Matching +full:mode +full:- +full:capable
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
64 #define IGC_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
149 #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */
150 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
151 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
233 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
771 #define IGC_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
835 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
840 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
841 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
842 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
843 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
844 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
845 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
846 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
850 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
851 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
852 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
853 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
854 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
862 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
863 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
864 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
865 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
866 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
875 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
876 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
877 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
878 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
899 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
900 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1125 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1190 /* Kumeran Mode Control */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out