Lines Matching refs:RegKind
123 unsigned RegKind : 4; member
189 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
194 Op->Mem.RegKind = RegKind; in createMem()
227 bool isReg(RegisterKind RegKind) const { in isReg()
228 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
268 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
269 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
271 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12()
272 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true); in isMemDisp12()
274 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20()
275 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true); in isMemDisp20()
277 bool isMemDisp12Len4(RegisterKind RegKind) const { in isMemDisp12Len4()
278 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); in isMemDisp12Len4()
280 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
281 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); in isMemDisp12Len8()
437 RegisterKind RegKind);
1099 RegisterKind RegKind) { in parseAddress() argument
1114 switch (RegKind) { in parseAddress()
1193 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, in parseAddress()