Lines Matching refs:MVT
140 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
260 return DAG.getNode(HexagonISD::RET_GLUE, dl, MVT::Other, RetOps); in LowerReturn()
368 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
376 MVT::i32, Glue); in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
636 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in getPostIndexedAddressParts()
637 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 || in getPostIndexedAddressParts()
638 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 || in getPostIndexedAddressParts()
639 VT == MVT::v4i16 || VT == MVT::v8i8 || in getPostIndexedAddressParts()
675 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue) in LowerINLINEASM()
719 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerPREFETCH()
720 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero); in LowerPREFETCH()
731 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); in LowerREADCYCLECOUNTER()
743 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); in LowerREADSTEADYCOUNTER()
755 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerINTRINSIC_VOID()
756 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero); in LowerINTRINSIC_VOID()
784 SDValue AC = DAG.getConstant(A, dl, MVT::i32); in LowerDYNAMIC_STACKALLOC()
785 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); in LowerDYNAMIC_STACKALLOC()
857 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
868 if (VA.getValVT() == MVT::i1) { in LowerFormalArguments()
872 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
896 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); in LowerFormalArguments()
968 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); in LowerVASTART()
990 DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32); in LowerVASTART()
998 MVT::i32), in LowerVASTART()
1026 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in LowerVASTART()
1052 MVT ResTy = ty(Op); in LowerSETCC()
1053 MVT OpTy = ty(LHS); in LowerSETCC()
1055 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerSETCC()
1056 MVT ElemTy = OpTy.getVectorElementType(); in LowerSETCC()
1058 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()), in LowerSETCC()
1094 if (OpTy == MVT::i8 || OpTy == MVT::i16) { in LowerSETCC()
1099 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32), in LowerSETCC()
1100 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC); in LowerSETCC()
1110 MVT OpTy = ty(Op1); in LowerVSELECT()
1113 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) { in LowerVSELECT()
1114 MVT ElemTy = OpTy.getVectorElementType(); in LowerVSELECT()
1116 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()), in LowerVSELECT()
1200 SDValue Offset = DAG.getConstant(4, dl, MVT::i32); in LowerRETURNADDR()
1207 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1231 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
1263 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32); in LowerGLOBALADDRESS()
1299 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in GetDynamicTLSAddr()
1484 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering()
1485 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1486 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa in HexagonTargetLowering()
1487 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1488 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1489 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1490 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1491 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1492 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1493 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1494 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1496 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering()
1497 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1511 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in HexagonTargetLowering()
1512 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in HexagonTargetLowering()
1513 setOperationAction(ISD::TRAP, MVT::Other, Legal); in HexagonTargetLowering()
1514 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in HexagonTargetLowering()
1515 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in HexagonTargetLowering()
1516 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
1517 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
1518 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in HexagonTargetLowering()
1519 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in HexagonTargetLowering()
1520 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in HexagonTargetLowering()
1521 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in HexagonTargetLowering()
1522 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Custom); in HexagonTargetLowering()
1523 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
1524 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); in HexagonTargetLowering()
1525 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); in HexagonTargetLowering()
1526 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in HexagonTargetLowering()
1527 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in HexagonTargetLowering()
1530 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in HexagonTargetLowering()
1531 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); in HexagonTargetLowering()
1532 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in HexagonTargetLowering()
1535 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1536 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1537 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1538 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1541 setOperationAction(ISD::VASTART, MVT::Other, Custom); in HexagonTargetLowering()
1542 setOperationAction(ISD::VAEND, MVT::Other, Expand); in HexagonTargetLowering()
1543 setOperationAction(ISD::VAARG, MVT::Other, Expand); in HexagonTargetLowering()
1545 setOperationAction(ISD::VACOPY, MVT::Other, Custom); in HexagonTargetLowering()
1547 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in HexagonTargetLowering()
1549 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in HexagonTargetLowering()
1550 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in HexagonTargetLowering()
1551 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in HexagonTargetLowering()
1557 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in HexagonTargetLowering()
1561 setOperationAction(LegalIntOp, MVT::i32, Legal); in HexagonTargetLowering()
1562 setOperationAction(LegalIntOp, MVT::i64, Legal); in HexagonTargetLowering()
1567 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1575 setOperationAction(ISD::UADDO_CARRY, MVT::i64, Custom); in HexagonTargetLowering()
1576 setOperationAction(ISD::USUBO_CARRY, MVT::i64, Custom); in HexagonTargetLowering()
1578 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1579 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1580 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1581 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1584 setOperationAction(ISD::CTPOP, MVT::i8, Promote); in HexagonTargetLowering()
1585 setOperationAction(ISD::CTPOP, MVT::i16, Promote); in HexagonTargetLowering()
1586 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in HexagonTargetLowering()
1587 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1589 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1590 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1591 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
1592 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in HexagonTargetLowering()
1594 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1595 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
1596 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1597 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
1604 for (MVT VT : MVT::integer_valuetypes()) in HexagonTargetLowering()
1611 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering()
1616 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1622 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in HexagonTargetLowering()
1624 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering()
1625 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1628 for (MVT VT : MVT::integer_valuetypes()) { in HexagonTargetLowering()
1632 for (MVT VT : MVT::fp_valuetypes()) { in HexagonTargetLowering()
1636 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
1669 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in HexagonTargetLowering()
1674 for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) { in HexagonTargetLowering()
1684 if (VT.getVectorElementType() != MVT::i32) { in HexagonTargetLowering()
1685 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32); in HexagonTargetLowering()
1696 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1697 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1698 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1699 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1700 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1701 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1703 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in HexagonTargetLowering()
1704 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1705 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in HexagonTargetLowering()
1708 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8, in HexagonTargetLowering()
1709 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1724 if (NativeVT.getVectorElementType() != MVT::i1) { in HexagonTargetLowering()
1731 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1742 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8, in HexagonTargetLowering()
1743 MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1749 for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) { in HexagonTargetLowering()
1755 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1756 MVT::v2i32}) { in HexagonTargetLowering()
1767 for (MVT VT : {MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1}) { in HexagonTargetLowering()
1775 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in HexagonTargetLowering()
1776 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1777 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1778 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1781 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
1784 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering()
1785 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1786 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1787 setOperationAction(ISD::FMUL, MVT::f64, Expand); in HexagonTargetLowering()
1788 setOperationAction(ISD::FDIV, MVT::f32, Custom); in HexagonTargetLowering()
1790 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
1791 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1793 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
1794 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); in HexagonTargetLowering()
1795 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); in HexagonTargetLowering()
1796 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1797 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1798 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1799 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1800 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1801 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1802 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1803 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1804 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1808 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in HexagonTargetLowering()
1809 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in HexagonTargetLowering()
1810 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in HexagonTargetLowering()
1811 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in HexagonTargetLowering()
1813 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in HexagonTargetLowering()
1814 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in HexagonTargetLowering()
1815 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in HexagonTargetLowering()
1816 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in HexagonTargetLowering()
1820 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64, in HexagonTargetLowering()
1821 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) { in HexagonTargetLowering()
1829 setOperationAction(ISD::ROTL, MVT::i32, Legal); in HexagonTargetLowering()
1830 setOperationAction(ISD::ROTL, MVT::i64, Legal); in HexagonTargetLowering()
1831 setOperationAction(ISD::ROTR, MVT::i32, Legal); in HexagonTargetLowering()
1832 setOperationAction(ISD::ROTR, MVT::i64, Legal); in HexagonTargetLowering()
1835 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering()
1836 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()
1839 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in HexagonTargetLowering()
1840 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
1841 setOperationAction(ISD::FMUL, MVT::f64, Legal); in HexagonTargetLowering()
2011 SDValue Trap = DAG.getNode(ISD::TRAP, dl, MVT::Other, Chain); in replaceMemWithUndef()
2114 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2139 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
2166 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
2186 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
2187 if (ResTy.getVectorElementType() != MVT::i1) in isExtractSubvectorCheap()
2205 HexagonTargetLowering::getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
2207 MVT ElemTy = VT.getVectorElementType(); in getPreferredVectorAction()
2219 if (ElemTy == MVT::i1) in getPreferredVectorAction()
2260 MVT VecTy = ty(Op); in LowerVECTOR_SHUFFLE()
2321 SDValue T0 = DAG.getBitcast(MVT::i32, Op0); in LowerVECTOR_SHUFFLE()
2322 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0); in LowerVECTOR_SHUFFLE()
2348 SDValue T0 = DAG.getBitcast(MVT::i64, Op0); in LowerVECTOR_SHUFFLE()
2349 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0); in LowerVECTOR_SHUFFLE()
2436 MVT ResTy = ty(Res); in LowerVECTOR_SHIFT()
2437 if (ResTy.getVectorElementType() != MVT::i8) in LowerVECTOR_SHIFT()
2441 assert(ResTy.getVectorElementType() == MVT::i8); in LowerVECTOR_SHIFT()
2445 MVT Ty = ty(V); in LowerVECTOR_SHIFT()
2446 MVT ExtTy = MVT::getVectorVT(MVT::i16, Ty.getVectorNumElements()); in LowerVECTOR_SHIFT()
2470 MVT ResTy = ty(Op); in LowerBITCAST()
2472 MVT InpTy = ty(InpV); in LowerBITCAST()
2477 if (InpTy == MVT::i8) { in LowerBITCAST()
2478 if (ResTy == MVT::v8i1) { in LowerBITCAST()
2480 SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32); in LowerBITCAST()
2491 MVT VecTy, SelectionDAG &DAG, in getBuildVectorConstInts()
2493 MVT ElemTy = VecTy.getVectorElementType(); in getBuildVectorConstInts()
2521 MVT VecTy, SelectionDAG &DAG) const { in buildVector32()
2522 MVT ElemTy = VecTy.getVectorElementType(); in buildVector32()
2540 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { in buildVector32()
2547 return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32)); in buildVector32()
2550 if (ElemTy == MVT::f16) { in buildVector32()
2551 E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32); in buildVector32()
2552 E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32); in buildVector32()
2557 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG); in buildVector32()
2561 if (ElemTy == MVT::i8) { in buildVector32()
2568 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32)); in buildVector32()
2581 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32); in buildVector32()
2591 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32); in buildVector32()
2592 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2594 SDValue S8 = DAG.getConstant(8, dl, MVT::i32); in buildVector32()
2595 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8}); in buildVector32()
2596 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8}); in buildVector32()
2597 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0}); in buildVector32()
2598 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1}); in buildVector32()
2600 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG); in buildVector32()
2601 return DAG.getBitcast(MVT::v4i8, R); in buildVector32()
2612 MVT VecTy, SelectionDAG &DAG) const { in buildVector64()
2613 MVT ElemTy = VecTy.getVectorElementType(); in buildVector64()
2632 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { in buildVector64()
2642 SDValue S = ElemTy == MVT::f16 ? DAG.getBitcast(MVT::i16, Elem[First]) in buildVector64()
2644 SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32); in buildVector64()
2656 SDValue V0 = DAG.getConstant(Val, dl, MVT::i64); in buildVector64()
2661 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2); in buildVector64()
2662 SDValue L = (ElemTy == MVT::i32) in buildVector64()
2665 SDValue H = (ElemTy == MVT::i32) in buildVector64()
2673 const SDLoc &dl, MVT ValTy, MVT ResTy, in extractVector()
2675 MVT VecTy = ty(VecV); in extractVector()
2678 if (VecTy.getVectorElementType() == MVT::i1) in extractVector()
2688 MVT ScalarTy = tyScalar(VecTy); in extractVector()
2691 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32); in extractVector()
2702 SDValue OffV = DAG.getConstant(Off, dl, MVT::i32); in extractVector()
2709 if (ty(IdxV) != MVT::i32) in extractVector()
2710 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in extractVector()
2711 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVector()
2712 DAG.getConstant(ElemWidth, dl, MVT::i32)); in extractVector()
2725 const SDLoc &dl, MVT ValTy, MVT ResTy, in extractVectorPred()
2729 MVT VecTy = ty(VecV); in extractVectorPred()
2741 return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV); in extractVectorPred()
2746 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG); in extractVectorPred()
2747 SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32); in extractVectorPred()
2748 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0); in extractVectorPred()
2749 return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0); in extractVectorPred()
2760 assert(ty(IdxV) == MVT::i32); in extractVectorPred()
2762 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVectorPred()
2763 DAG.getConstant(8*VecRep, dl, MVT::i32)); in extractVectorPred()
2764 SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV); in extractVectorPred()
2765 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0); in extractVectorPred()
2779 const SDLoc &dl, MVT ValTy, in insertVector()
2781 MVT VecTy = ty(VecV); in insertVector()
2782 if (VecTy.getVectorElementType() == MVT::i1) in insertVector()
2791 MVT ScalarTy = MVT::getIntegerVT(VecWidth); in insertVector()
2795 ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV); in insertVector()
2800 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32); in insertVector()
2805 SDValue OffV = DAG.getConstant(W, dl, MVT::i32); in insertVector()
2809 if (ty(IdxV) != MVT::i32) in insertVector()
2810 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32); in insertVector()
2811 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV); in insertVector()
2822 MVT ValTy, SelectionDAG &DAG) const { in insertVectorPred()
2823 MVT VecTy = ty(VecV); in insertVectorPred()
2826 if (ValTy == MVT::i1) { in insertVectorPred()
2827 SDValue ToReg = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG); in insertVectorPred()
2828 SDValue Ext = DAG.getSExtOrTrunc(ValV, dl, MVT::i32); in insertVectorPred()
2829 SDValue Width = DAG.getConstant(8 / VecLen, dl, MVT::i32); in insertVectorPred()
2830 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width); in insertVectorPred()
2832 DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, {ToReg, Ext, Width, Idx}); in insertVectorPred()
2836 assert(ValTy.getVectorElementType() == MVT::i1); in insertVectorPred()
2838 ? DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV) in insertVectorPred()
2839 : DAG.getSExtOrTrunc(ValV, dl, MVT::i64); in insertVectorPred()
2846 ValR = getCombine(DAG.getUNDEF(MVT::i32), ValR, dl, MVT::i64, DAG); in insertVectorPred()
2849 SDValue Width = DAG.getConstant(64 / Scale, dl, MVT::i32); in insertVectorPred()
2850 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, Width); in insertVectorPred()
2851 SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV); in insertVectorPred()
2853 DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, {VecR, ValR, Width, Idx}); in insertVectorPred()
2862 return DAG.getUNDEF(MVT::i64); in expandPredicate()
2863 SDValue P = DAG.getBitcast(MVT::v4i8, Vec32); in expandPredicate()
2864 SDValue X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i16, P); in expandPredicate()
2865 return DAG.getBitcast(MVT::i64, X); in expandPredicate()
2873 return DAG.getUNDEF(MVT::i32); in contractPredicate()
2875 SDValue A = DAG.getBitcast(MVT::v8i8, Vec64); in contractPredicate()
2876 SDValue S = DAG.getVectorShuffle(MVT::v8i8, dl, A, DAG.getUNDEF(MVT::v8i8), in contractPredicate()
2878 return extractVector(S, DAG.getConstant(0, dl, MVT::i32), dl, MVT::v4i8, in contractPredicate()
2879 MVT::i32, DAG); in contractPredicate()
2883 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) in getZero()
2888 return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W))); in getZero()
2889 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
2900 HexagonTargetLowering::appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) in appendUndef()
2902 MVT ValTy = ty(Val); in appendUndef()
2923 MVT ResTy, SelectionDAG &DAG) const { in getCombine()
2924 MVT ElemTy = ty(Hi); in getCombine()
2929 MVT PairTy = MVT::getIntegerVT(2 * ElemTy.getSizeInBits()); in getCombine()
2935 MVT IntTy = MVT::getIntegerVT(Width); in getCombine()
2936 MVT PairTy = MVT::getIntegerVT(2 * Width); in getCombine()
2945 MVT VecTy = ty(Op); in LowerBUILD_VECTOR()
2957 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) { in LowerBUILD_VECTOR()
2979 SDValue Z = getZero(dl, MVT::i32, DAG); in LowerBUILD_VECTOR()
2983 SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32); in LowerBUILD_VECTOR()
2984 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z); in LowerBUILD_VECTOR()
2988 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]); in LowerBUILD_VECTOR()
3000 MVT VecTy = ty(Op); in LowerCONCAT_VECTORS()
3007 MVT ElemTy = VecTy.getVectorElementType(); in LowerCONCAT_VECTORS()
3008 if (ElemTy == MVT::i1) { in LowerCONCAT_VECTORS()
3009 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1); in LowerCONCAT_VECTORS()
3010 MVT OpTy = ty(Op.getOperand(0)); in LowerCONCAT_VECTORS()
3024 SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P); in LowerCONCAT_VECTORS()
3027 W = getCombine(DAG.getUNDEF(MVT::i32), W, dl, MVT::i64, DAG); in LowerCONCAT_VECTORS()
3034 SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32); in LowerCONCAT_VECTORS()
3040 SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, in LowerCONCAT_VECTORS()
3051 SDValue WW = getCombine(Words[IdxW][1], Words[IdxW][0], dl, MVT::i64, DAG); in LowerCONCAT_VECTORS()
3062 MVT ElemTy = ty(Vec).getVectorElementType(); in LowerEXTRACT_VECTOR_ELT()
3103 MVT Ty = ty(Op); in LowerLoad()
3106 MVT MemTy = LN->getMemoryVT().getSimpleVT(); in LowerLoad()
3109 bool LoadPred = MemTy == MVT::v2i1 || MemTy == MVT::v4i1 || MemTy == MVT::v8i1; in LowerLoad()
3112 LN->getAddressingMode(), ISD::ZEXTLOAD, MVT::i32, dl, LN->getChain(), in LowerLoad()
3114 /*MemoryVT*/ MVT::i8, LN->getAlign(), LN->getMemOperand()->getFlags(), in LowerLoad()
3144 MVT Ty = ty(Val); in LowerStore()
3146 if (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1) { in LowerStore()
3148 SDValue TR = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {Val}, DAG); in LowerStore()
3150 MVT::i8, SN->getMemOperand()); in LowerStore()
3162 MVT StoreTy = SN->getMemoryVT().getSimpleVT(); in LowerStore()
3173 MVT LoadTy = ty(Op); in LowerUnalignedLoad()
3198 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) in LowerUnalignedLoad()
3199 : MVT::getVectorVT(MVT::i8, HaveAlign); in LowerUnalignedLoad()
3224 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
3225 DAG.getConstant(BO.second % LoadLen, dl, MVT::i32)); in LowerUnalignedLoad()
3229 ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
3230 DAG.getConstant(NeedAlign, dl, MVT::i32)) in LowerUnalignedLoad()
3251 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in LowerUnalignedLoad()
3267 assert(VTs.VTs[1] == MVT::i1); in LowerUAddSubO()
3279 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG), in LowerUAddSubO()
3285 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, in LowerUAddSubO()
3336 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain); in LowerEH_RETURN()
3457 if (N->getValueType(0) == MVT::i8) { in ReplaceNodeResults()
3458 if (N->getOperand(0).getValueType() == MVT::v8i1) { in ReplaceNodeResults()
3459 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, in ReplaceNodeResults()
3461 SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8); in ReplaceNodeResults()
3527 MVT TruncTy = ty(Op); in PerformDAGCombine()
3540 if (ty(Op) != MVT::i64) in PerformDAGCombine()
3556 DCI.DAG.getConstant(A - 32, dl, MVT::i32)); in PerformDAGCombine()
3557 SDValue T1 = DCI.DAG.getZExtOrTrunc(T0, dl, MVT::i32); in PerformDAGCombine()
3558 SDValue T2 = DCI.DAG.getZExtOrTrunc(Z, dl, MVT::i32); in PerformDAGCombine()
3559 return DCI.DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {T1, T2}); in PerformDAGCombine()
3605 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
3613 case MVT::i1: in getRegForInlineAsmConstraint()
3614 case MVT::i8: in getRegForInlineAsmConstraint()
3615 case MVT::i16: in getRegForInlineAsmConstraint()
3616 case MVT::i32: in getRegForInlineAsmConstraint()
3617 case MVT::f32: in getRegForInlineAsmConstraint()
3619 case MVT::i64: in getRegForInlineAsmConstraint()
3620 case MVT::f64: in getRegForInlineAsmConstraint()
3625 if (VT != MVT::i32) in getRegForInlineAsmConstraint()
3788 return MVT::i64; in getOptimalMemOpType()
3790 return MVT::i32; in getOptimalMemOpType()
3792 return MVT::i16; in getOptimalMemOpType()
3793 return MVT::Other; in getOptimalMemOpType()
3801 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess()
3813 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses()
3823 MVT VT) const { in findRepresentativeClass()
3828 if (VT.getVectorElementType() == MVT::i1) in findRepresentativeClass()