393                                         Register SrcReg, bool IsKill, int FI,  in storeRegToStackSlot()  argument
429       .addReg(SrcReg, getKillRegState(IsKill))  in storeRegToStackSlot()
481                                 MCRegister SrcReg, bool KillSrc) const {  in copyPhysReg()  argument
482   if (CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
486           .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
489       assert(SrcReg < CSKY::R8);  in copyPhysReg()
491           .addReg(SrcReg, getKillRegState(KillSrc))  in copyPhysReg()
497   if (CSKY::CARRYRegClass.contains(SrcReg) &&  in copyPhysReg()
502           .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()
509           .addReg(SrcReg, RegState::Define)  in copyPhysReg()
512           .addReg(SrcReg, getKillRegState(true));  in copyPhysReg()
514           .addReg(SrcReg, RegState::Define | getDeadRegState(KillSrc))  in copyPhysReg()
522   if (CSKY::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
524   else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
526   else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
528   else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
530   else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
532   else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
535   else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
538   else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) &&  in copyPhysReg()
541   else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) &&  in copyPhysReg()
544   else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
547   else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
550   else if (v2df && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
553   else if (v3df && CSKY::GPRRegClass.contains(SrcReg) &&  in copyPhysReg()
557     LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg);  in copyPhysReg()
563       .addReg(SrcReg, getKillRegState(KillSrc));  in copyPhysReg()