Lines Matching refs:Rd
1549 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1556 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1557 iii, opc, "\t$Rd, $Rn, $imm",
1558 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1560 bits<4> Rd;
1565 let Inst{15-12} = Rd;
1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1570 iir, opc, "\t$Rd, $Rn, $Rm",
1571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1573 bits<4> Rd;
1579 let Inst{15-12} = Rd;
1584 def rsi : AsI1<opcod, (outs GPR:$Rd),
1586 iis, opc, "\t$Rd, $Rn, $shift",
1587 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1589 bits<4> Rd;
1594 let Inst{15-12} = Rd;
1600 def rsr : AsI1<opcod, (outs GPR:$Rd),
1602 iis, opc, "\t$Rd, $Rn, $shift",
1603 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1605 bits<4> Rd;
1610 let Inst{15-12} = Rd;
1622 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1629 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1630 iii, opc, "\t$Rd, $Rn, $imm",
1631 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1633 bits<4> Rd;
1638 let Inst{15-12} = Rd;
1642 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1643 iir, opc, "\t$Rd, $Rn, $Rm",
1646 bits<4> Rd;
1652 let Inst{15-12} = Rd;
1656 def rsi : AsI1<opcod, (outs GPR:$Rd),
1658 iis, opc, "\t$Rd, $Rn, $shift",
1659 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1661 bits<4> Rd;
1666 let Inst{15-12} = Rd;
1672 def rsr : AsI1<opcod, (outs GPR:$Rd),
1674 iis, opc, "\t$Rd, $Rn, $shift",
1675 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1677 bits<4> Rd;
1682 let Inst{15-12} = Rd;
1699 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1701 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1704 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1710 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1713 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1717 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1720 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1731 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1733 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1736 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1739 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1743 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1746 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1835 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1836 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1837 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1839 bits<4> Rd;
1843 let Inst{15-12} = Rd;
1849 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1850 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1860 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1861 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1862 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1865 bits<4> Rd;
1870 let Inst{15-12} = Rd;
1877 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1878 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1887 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1891 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1892 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1893 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1896 bits<4> Rd;
1900 let Inst{15-12} = Rd;
1904 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1905 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1906 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1909 bits<4> Rd;
1916 let Inst{15-12} = Rd;
1919 def rsi : AsI1<opcod, (outs GPR:$Rd),
1921 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1922 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1925 bits<4> Rd;
1930 let Inst{15-12} = Rd;
1935 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1937 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1938 [(set GPRnopc:$Rd, CPSR,
1942 bits<4> Rd;
1947 let Inst{15-12} = Rd;
1958 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1961 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1962 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1963 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1966 bits<4> Rd;
1970 let Inst{15-12} = Rd;
1974 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1975 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1978 bits<4> Rd;
1984 let Inst{15-12} = Rd;
1987 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1988 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1989 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1992 bits<4> Rd;
1997 let Inst{15-12} = Rd;
2002 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2003 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
2004 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
2007 bits<4> Rd;
2012 let Inst{15-12} = Rd;
2223 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2224 "\t$Rd, $Rn, $Rm",
2225 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2227 bits<4> Rd;
2231 let Inst{15-12} = Rd;
2443 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2444 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2446 bits<4> Rd;
2454 let Inst{15-12} = Rd;
2459 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2462 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
3606 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3607 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3608 bits<4> Rd;
3615 let Inst{15-12} = Rd;
3620 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3621 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3622 bits<4> Rd;
3628 let Inst{15-12} = Rd;
3631 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3633 "mov", "\t$Rd, $src",
3634 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3636 bits<4> Rd;
3638 let Inst{15-12} = Rd;
3648 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3650 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3652 bits<4> Rd;
3654 let Inst{15-12} = Rd;
3663 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3664 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3666 bits<4> Rd;
3669 let Inst{15-12} = Rd;
3675 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3677 "movw", "\t$Rd, $imm",
3678 [(set GPR:$Rd, imm0_65535:$imm)]>,
3680 bits<4> Rd;
3682 let Inst{15-12} = Rd;
3690 def : InstAlias<"mov${p} $Rd, $imm",
3691 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3696 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3700 let Constraints = "$src = $Rd" in {
3701 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3704 "movt", "\t$Rd, $imm",
3705 [(set GPRnopc:$Rd,
3709 bits<4> Rd;
3711 let Inst{15-12} = Rd;
3721 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3731 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3732 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3823 def SBFX : I<(outs GPRnopc:$Rd),
3826 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3828 bits<4> Rd;
3835 let Inst{15-12} = Rd;
3840 def UBFX : I<(outs GPRnopc:$Rd),
3843 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3845 bits<4> Rd;
3852 let Inst{15-12} = Rd;
3932 string asm = "\t$Rd, $Rn, $Rm">
3933 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3936 bits<4> Rd;
3941 let Inst{15-12} = Rd;
3953 "\t$Rd, $Rm, $Rn">;
3958 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3968 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm,
3971 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
3974 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3977 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
4049 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4051 "\t$Rd, $Rn, $Rm",
4052 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4054 bits<4> Rd;
4060 let Inst{19-16} = Rd;
4064 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4066 "\t$Rd, $Rn, $Rm, $Ra",
4067 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4069 bits<4> Rd;
4075 let Inst{19-16} = Rd;
4082 def SSAT : AI<(outs GPRnopc:$Rd),
4084 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4086 bits<4> Rd;
4093 let Inst{15-12} = Rd;
4099 def SSAT16 : AI<(outs GPRnopc:$Rd),
4101 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
4103 bits<4> Rd;
4108 let Inst{15-12} = Rd;
4113 def USAT : AI<(outs GPRnopc:$Rd),
4115 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4117 bits<4> Rd;
4123 let Inst{15-12} = Rd;
4130 def USAT16 : AI<(outs GPRnopc:$Rd),
4132 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
4134 bits<4> Rd;
4139 let Inst{15-12} = Rd;
4192 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
4194 "bfc", "\t$Rd, $imm", "$src = $Rd",
4195 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
4197 bits<4> Rd;
4201 let Inst{15-12} = Rd;
4207 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4209 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
4210 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4213 bits<4> Rd;
4218 let Inst{15-12} = Rd;
4224 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4225 "mvn", "\t$Rd, $Rm",
4226 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4227 bits<4> Rd;
4232 let Inst{15-12} = Rd;
4237 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
4238 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
4239 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
4241 bits<4> Rd;
4245 let Inst{15-12} = Rd;
4252 def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
4253 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
4254 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
4256 bits<4> Rd;
4260 let Inst{15-12} = Rd;
4270 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
4271 IIC_iMVNi, "mvn", "\t$Rd, $imm",
4272 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4273 bits<4> Rd;
4277 let Inst{15-12} = Rd;
4291 bits<4> Rd;
4294 let Inst{19-16} = Rd;
4326 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
4327 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
4329 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
4330 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
4337 let Constraints = "@earlyclobber $Rd" in
4338 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
4341 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
4342 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
4347 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
4349 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4350 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4357 let Constraints = "@earlyclobber $Rd" in
4358 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
4361 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4362 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4366 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4367 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4368 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4371 bits<4> Rd;
4375 let Inst{19-16} = Rd;
4470 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4471 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4472 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4478 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4479 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
4480 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4486 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4488 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4489 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4493 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4495 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
4496 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4500 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4502 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4506 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4508 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
4509 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4514 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4515 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4516 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4520 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4521 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4522 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4526 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4527 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4528 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4532 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4533 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4534 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4538 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4539 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4540 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4544 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4545 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4546 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4554 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4556 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4557 [(set GPRnopc:$Rd, (add GPR:$Ra,
4562 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4564 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4565 [(set GPRnopc:$Rd, (add GPR:$Ra,
4570 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4572 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4573 [(set GPRnopc:$Rd, (add GPR:$Ra,
4578 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4580 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4581 [(set GPRnopc:$Rd, (add GPR:$Ra,
4586 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4588 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4589 [(set GPRnopc:$Rd,
4594 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4596 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4597 [(set GPRnopc:$Rd,
4651 bits<4> Rd;
4653 let Inst{19-16} = Rd;
4659 bits<4> Rd;
4660 let Inst{19-16} = Rd;
4674 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4676 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4679 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4681 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4721 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4722 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4724 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4725 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4744 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4745 "sdiv", "\t$Rd, $Rn, $Rm",
4746 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4750 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4751 "udiv", "\t$Rd, $Rn, $Rm",
4752 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4760 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4761 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4762 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4765 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4766 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4767 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4771 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4772 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4773 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4777 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4778 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4779 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4791 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4792 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4793 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4801 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4803 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4804 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4818 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4820 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4821 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4850 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4851 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4852 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4854 bits<4> Rd;
4863 let Inst{15-12} = Rd;
5040 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
5043 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
5045 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5047 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
5050 [(set GPR:$Rd,
5053 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5054 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
5057 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
5059 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5064 : ARMPseudoInst<(outs GPR:$Rd),
5067 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
5069 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
5073 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
5076 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
5078 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5083 : ARMPseudoInst<(outs GPR:$Rd),
5086 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
5088 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
5091 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
5094 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
5096 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5290 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
5291 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5292 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
5293 [(set GPR:$Rd, (strex_1 GPR:$Rt,
5295 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5296 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
5297 [(set GPR:$Rd, (strex_2 GPR:$Rt,
5299 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5300 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
5301 [(set GPR:$Rd, (strex_4 GPR:$Rt,
5304 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
5306 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
5309 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5310 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
5311 [(set GPR:$Rd,
5313 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5314 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
5315 [(set GPR:$Rd,
5317 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5318 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
5319 [(set GPR:$Rd,
5322 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
5324 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
5779 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5780 "mrs", "\t$Rd, apsr", []> {
5781 bits<4> Rd;
5785 let Inst{15-12} = Rd;
5791 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
5796 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5797 "mrs", "\t$Rd, spsr", []> {
5798 bits<4> Rd;
5802 let Inst{15-12} = Rd;
5810 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5811 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5814 bits<4> Rd;
5820 let Inst{15-12} = Rd;
6263 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
6264 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
6266 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
6267 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
6275 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
6276 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6277 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
6278 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6282 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
6283 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6284 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
6285 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6286 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
6287 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6288 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
6289 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6290 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
6291 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6292 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
6293 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6295 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
6296 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6297 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
6298 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6299 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
6300 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6301 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
6302 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6303 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
6304 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6305 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
6306 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6346 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
6348 def : ARMInstSubst<"mov${s}${p} $Rd, $imm",
6349 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6350 def : ARMInstSubst<"mvn${s}${p} $Rd, $imm",
6351 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6353 def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
6354 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6359 def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
6360 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6366 // Likewise, "add Rd, mod_imm_neg" -> sub
6367 def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
6368 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6369 def : ARMInstSubst<"add${s}${p} $Rd, $imm",
6370 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6371 // Likewise, "sub Rd, mod_imm_neg" -> add
6372 def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
6373 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6374 def : ARMInstSubst<"sub${s}${p} $Rd, $imm",
6375 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6378 def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
6379 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6382 def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
6383 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6388 def : ARMInstSubst<"cmp${p} $Rd, $imm",
6389 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
6390 def : ARMInstSubst<"cmn${p} $Rd, $imm",
6391 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
6398 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
6399 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
6400 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6402 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
6403 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6405 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
6406 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6408 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
6409 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6412 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
6413 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6414 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
6415 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
6416 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6418 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
6419 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6421 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
6422 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6424 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
6425 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6430 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
6431 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6440 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6441 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6443 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6444 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6465 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6467 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
6496 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
6498 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6502 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6506 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6510 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),