Lines Matching refs:MIRBuilder
39 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
81 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
86 auto ToSGPR = MIRBuilder in assignValueToReg()
93 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
107 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in getStackAddress()
113 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); in getStackAddress()
114 auto AddrReg = MIRBuilder.buildFrameIndex( in getStackAddress()
127 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
133 MIRBuilder.buildTrunc(ValVReg, Extended); in assignValueToReg()
143 MachineFunction &MF = MIRBuilder.getMF(); in assignValueToAddress()
148 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
162 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
167 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
169 : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
188 AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder, in AMDGPUOutgoingArgHandler()
191 : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff), in AMDGPUOutgoingArgHandler()
197 MachineFunction &MF = MIRBuilder.getMF(); in getStackAddress()
204 auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI); in getStackAddress()
212 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>(); in getStackAddress()
215 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
221 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy}, in getStackAddress()
226 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
228 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
237 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
243 MachineFunction &MF = MIRBuilder.getMF(); in assignValueToAddress()
250 MIRBuilder.buildStore(ValVReg, Addr, *MMO); in assignValueToAddress()
750 bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder, in passSpecialInputs() argument
754 MachineFunction &MF = MIRBuilder.getMF(); in passSpecialInputs()
823 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
825 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder); in passSpecialInputs()
830 MIRBuilder.buildConstant(InputReg, *Id); in passSpecialInputs()
832 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
837 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
890 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX, in passSpecialInputs()
893 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
900 LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY), in passSpecialInputs()
903 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
904 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y; in passSpecialInputs()
910 LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ), in passSpecialInputs()
913 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
914 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z; in passSpecialInputs()
925 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
932 LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg, in passSpecialInputs()
977 MachineIRBuilder &MIRBuilder, in addCallTargetOperands() argument
986 auto Ptr = MIRBuilder.buildGlobalValue( in addCallTargetOperands()
1156 MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, in handleImplicitCallArguments() argument
1163 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1170 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg); in handleImplicitCallArguments()
1175 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
1181 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, in lowerTailCall() argument
1183 MachineFunction &MF = MIRBuilder.getMF(); in lowerTailCall()
1201 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); in lowerTailCall()
1205 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerTailCall()
1206 if (!addCallTargetOperands(MIB, MIRBuilder, Info)) in lowerTailCall()
1290 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info)) in lowerTailCall()
1300 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff); in lowerTailCall()
1301 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder)) in lowerTailCall()
1307 handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, CalleeCC, in lowerTailCall()
1319 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0); in lowerTailCall()
1323 MIRBuilder.insertInstr(MIB); in lowerTailCall()
1343 bool AMDGPUCallLowering::lowerChainCall(MachineIRBuilder &MIRBuilder, in lowerChainCall() argument
1354 MachineFunction &MF = MIRBuilder.getMF(); in lowerChainCall()
1386 return lowerTailCall(MIRBuilder, Info, OutArgs); in lowerChainCall()
1389 bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall() argument
1395 return lowerChainCall(MIRBuilder, Info); in lowerCall()
1403 MachineFunction &MF = MIRBuilder.getMF(); in lowerCall()
1422 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs); in lowerCall()
1432 return lowerTailCall(MIRBuilder, Info, OutArgs); in lowerCall()
1440 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP) in lowerCall()
1449 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerCall()
1455 if (!addCallTargetOperands(MIB, MIRBuilder, Info)) in lowerCall()
1472 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info)) in lowerCall()
1483 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false); in lowerCall()
1484 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder)) in lowerCall()
1492 handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, Info.CallConv, in lowerCall()
1512 MIRBuilder.insertInstr(MIB); in lowerCall()
1521 CallReturnHandler Handler(MIRBuilder, MRI, MIB); in lowerCall()
1522 if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder, in lowerCall()
1529 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN) in lowerCall()
1534 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs, in lowerCall()