3440   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitStrictFPComparison()  local
3442   if ((VT == MVT::f16 && !FullFP16) || VT == MVT::bf16) {  in emitStrictFPComparison()
3458   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitComparison()  local
3462     if ((VT == MVT::f16 && !FullFP16) || VT == MVT::bf16) {  in emitComparison()
3567   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitConditionalComparison()  local
3571     if ((LHS.getValueType() == MVT::f16 && !FullFP16) ||  in emitConditionalComparison()
15111   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in LowerVSETCC()  local
15115   if ((!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) ||  in LowerVSETCC()
15127   assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||  in LowerVSETCC()
19135 static bool hasPairwiseAdd(unsigned Opcode, EVT VT, bool FullFP16) {  in hasPairwiseAdd()  argument
19139     return (FullFP16 && VT == MVT::f16) || VT == MVT::f32 || VT == MVT::f64;  in hasPairwiseAdd()
19247   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in performExtractVectorEltCombine()  local
19264   if (isNullConstant(N1) && hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&  in performExtractVectorEltCombine()