234     spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));  in cvmx_spi_reset_cb()
236     stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));  in cvmx_spi_reset_cb()
242     spxx_clk_ctl.u64 = 0;  in cvmx_spi_reset_cb()
244     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);  in cvmx_spi_reset_cb()
246     spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));  in cvmx_spi_reset_cb()
260         srxx_spi4_calx.u64 = 0;  in cvmx_spi_reset_cb()
262         cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), srxx_spi4_calx.u64);  in cvmx_spi_reset_cb()
264         stxx_spi4_calx.u64 = 0;  in cvmx_spi_reset_cb()
266         cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), stxx_spi4_calx.u64);  in cvmx_spi_reset_cb()
271     cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);  in cvmx_spi_reset_cb()
273     cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);  in cvmx_spi_reset_cb()
276     spxx_clk_ctl.u64 = 0;  in cvmx_spi_reset_cb()
286     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);  in cvmx_spi_reset_cb()
291     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);  in cvmx_spi_reset_cb()
307     cvmx_write_csr (CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);  in cvmx_spi_reset_cb()
309     spxx_dbg_deskew_ctl.u64 = 0;  in cvmx_spi_reset_cb()
310     cvmx_write_csr (CVMX_SPXX_DBG_DESKEW_CTL(interface), spxx_dbg_deskew_ctl.u64);  in cvmx_spi_reset_cb()
337         srxx_com_ctl.u64 = 0;  in cvmx_spi_calendar_setup_cb()
341         cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);  in cvmx_spi_calendar_setup_cb()
349             srxx_spi4_calx.u64 = 0;  in cvmx_spi_calendar_setup_cb()
354             srxx_spi4_calx.s.oddpar = ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);  in cvmx_spi_calendar_setup_cb()
355             cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), srxx_spi4_calx.u64);  in cvmx_spi_calendar_setup_cb()
358         srxx_spi4_stat.u64 = 0;  in cvmx_spi_calendar_setup_cb()
361         cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), srxx_spi4_stat.u64);  in cvmx_spi_calendar_setup_cb()
374         stxx_arb_ctl.u64 = 0;  in cvmx_spi_calendar_setup_cb()
377         cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);  in cvmx_spi_calendar_setup_cb()
379         gmxx_tx_spi_max.u64 = 0;  in cvmx_spi_calendar_setup_cb()
383         cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), gmxx_tx_spi_max.u64);  in cvmx_spi_calendar_setup_cb()
385         gmxx_tx_spi_thresh.u64 = 0;  in cvmx_spi_calendar_setup_cb()
387         cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), gmxx_tx_spi_thresh.u64);  in cvmx_spi_calendar_setup_cb()
389         gmxx_tx_spi_ctl.u64 = 0;  in cvmx_spi_calendar_setup_cb()
392         cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), gmxx_tx_spi_ctl.u64);  in cvmx_spi_calendar_setup_cb()
395         stxx_spi4_dat.u64 = 0;  in cvmx_spi_calendar_setup_cb()
398         cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), stxx_spi4_dat.u64);  in cvmx_spi_calendar_setup_cb()
406             stxx_spi4_calx.u64 = 0;  in cvmx_spi_calendar_setup_cb()
411             stxx_spi4_calx.s.oddpar = ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);  in cvmx_spi_calendar_setup_cb()
412             cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), stxx_spi4_calx.u64);  in cvmx_spi_calendar_setup_cb()
415         stxx_spi4_stat.u64 = 0;  in cvmx_spi_calendar_setup_cb()
418         cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), stxx_spi4_stat.u64);  in cvmx_spi_calendar_setup_cb()
452         stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));  in cvmx_spi_clock_detect_cb()
458             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);  in cvmx_spi_clock_detect_cb()
476         stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT(interface));  in cvmx_spi_clock_detect_cb()
482             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);  in cvmx_spi_clock_detect_cb()
518     spxx_clk_ctl.u64 = 0;  in cvmx_spi_training_cb()
528     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);  in cvmx_spi_training_cb()
532     spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));  in cvmx_spi_training_cb()
534     cvmx_write_csr (CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);  in cvmx_spi_training_cb()
548         stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT(interface));  in cvmx_spi_training_cb()
552             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);  in cvmx_spi_training_cb()
584         srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));  in cvmx_spi_calendar_sync_cb()
587         cvmx_write_csr (CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);  in cvmx_spi_calendar_sync_cb()
597         stxx_com_ctl.u64 = 0;  in cvmx_spi_calendar_sync_cb()
599         cvmx_write_csr (CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);  in cvmx_spi_calendar_sync_cb()
606             stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT (interface));  in cvmx_spi_calendar_sync_cb()
637         srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));  in cvmx_spi_interface_up_cb()
639         cvmx_write_csr (CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);  in cvmx_spi_interface_up_cb()
645         stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));  in cvmx_spi_interface_up_cb()
647         cvmx_write_csr (CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);  in cvmx_spi_interface_up_cb()
651     gmxx_rxx_frm_min.u64 = 0;  in cvmx_spi_interface_up_cb()
660     cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0,interface), gmxx_rxx_frm_min.u64);  in cvmx_spi_interface_up_cb()
661     gmxx_rxx_frm_max.u64 = 0;  in cvmx_spi_interface_up_cb()
663     cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0,interface), gmxx_rxx_frm_max.u64);  in cvmx_spi_interface_up_cb()
664     gmxx_rxx_jabber.u64 = 0;  in cvmx_spi_interface_up_cb()
666     cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0,interface), gmxx_rxx_jabber.u64);  in cvmx_spi_interface_up_cb()