Lines Matching refs:V2
1209 bits<5> V2;
1216 let Inst{35-32} = V2{3-0};
1222 let Inst{10} = V2{4};
1234 bits<5> V2;
1241 let Inst{35-32} = V2{3-0};
1246 let Inst{10} = V2{4};
1257 bits<5> V2;
1264 let Inst{35-32} = V2{3-0};
1270 let Inst{10} = V2{4};
1282 bits<5> V2;
1289 let Inst{35-32} = V2{3-0};
1294 let Inst{10} = V2{4};
1348 bits<5> V2;
1355 let Inst{35-32} = V2{3-0};
1364 let Inst{10} = V2{4};
1378 bits<5> V2;
1385 let Inst{35-32} = V2{3-0};
1395 let Inst{10} = V2{4};
1407 bits<5> V2;
1415 let Inst{35-32} = V2{3-0};
1422 let Inst{10} = V2{4};
1437 bits<5> V2;
1445 let Inst{35-32} = V2{3-0};
1455 let Inst{10} = V2{4};
1467 bits<5> V2;
1475 let Inst{35-32} = V2{3-0};
1482 let Inst{10} = V2{4};
1530 bits<5> V2;
1536 let Inst{31-28} = V2{3-0};
1542 let Inst{9} = V2{4};
1553 bits<5> V2;
1559 let Inst{35-32} = V2{3-0};
1565 let Inst{10} = V2{4};
1576 bits<5> V2;
1582 let Inst{35-32} = V2{3-0};
1589 let Inst{10} = V2{4};
1601 bits<5> V2;
1606 let Inst{35-32} = V2{3-0};
1613 let Inst{10} = V2{4};
1714 bits<5> V2;
1721 let Inst{35-32} = V2{3-0};
1726 let Inst{10} = V2{4};
3235 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
3236 mnemonic#"\t$V1, $V2",
3237 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> {
3247 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3248 mnemonic#"\t$V1, $V2, $M3", []> {
3255 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3256 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3270 (ins tr2.op:$V2, imm32zx4:$M5),
3271 mnemonic#"\t$V1, $V2, $M5", []>;
3272 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
3273 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
3274 def : InstAlias<mnemonic#"\t$V1, $V2",
3275 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
3284 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3285 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
3286 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
3287 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3882 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3883 mnemonic#"\t$V1, $V2, $I3",
3884 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3892 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3893 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
3902 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3903 mnemonic#"\t$V1, $V2, $M5",
3904 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3912 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3913 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3918 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3919 mnemonic#"\t$V1, $V2, $V3",
3920 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3927 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3928 mnemonic#"\t$V1, $V2, $V3, $M5", []> {
3934 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3935 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3952 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3953 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3967 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3968 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3969 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3970 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3971 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3972 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3981 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3982 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3983 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3984 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3991 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3992 mnemonic#"\t$V1, $V2, $V3",
3993 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4005 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
4006 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
4013 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4014 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
4034 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4036 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4045 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4046 mnemonic#"\t$R1, $V2, $M3", []> {
4051 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4052 mnemonic#"\t$V1, $V2, $M3", []>;
4164 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4367 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
4368 mnemonic#"\t$V1, $V2",
4369 [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> {
4379 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4380 mnemonic#"\t$V1, $V2, $M3", []> {
4388 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
4389 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
4395 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4396 mnemonic#"\t$V1, $V2, $M3", []> {
4638 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4639 mnemonic#"\t$V1, $V2, $V3, $I4",
4640 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4654 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
4655 mnemonic#"\t$V1, $V2, $M4, $M5",
4656 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4665 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4666 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4672 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4673 mnemonic#"\t$V1, $V2, $V3, $M5",
4674 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4691 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4692 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4697 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4698 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4705 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4706 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4707 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4708 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4715 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4716 mnemonic#"\t$V1, $V2, $V3, $M4",
4717 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4728 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4729 mnemonic#"\t$V1, $V2, $V3, $M6",
4730 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4739 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4741 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4746 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4747 mnemonic#"\t$V1, $V2, $V3, $V4",
4748 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4757 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4758 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4769 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4770 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>;
4771 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4773 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4774 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4775 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4782 (ins VR128:$V2, VR128:$V3, VR128:$V4,
4784 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4785 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4786 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4794 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4795 mnemonic#"\t$V1, $V2, $V3, $V4",
4796 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4807 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4808 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4824 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4826 mnemonic#"\t$R1, $V2, $M3, $M4", []>;
4829 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4831 mnemonic#"\t$V1, $V2, $V3, $M4", []>;
4845 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4870 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4871 mnemonic#"\t$V1, $V2, $V3, $I4",
4873 (tr2.vt tr2.op:$V2),
4883 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4885 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4892 (ins VR128:$V2, VR128:$V3,
4894 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4898 (ins VR128:$V2, imm32zx8:$I3,
4900 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>;
4907 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4908 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4909 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4919 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4920 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4933 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4934 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4940 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4941 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4948 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4949 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
5397 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
5398 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;